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1 ArF(193 nm) CoO(Cost of Owership) CD(Critical Dimension) (Difficult Challenges) (Potential Solutions) 15 ITWG International technology working group[ ] FEP(Front End Processing) ESH Environment, Safety, and Health[ ] TWG CD CD CD (Overlay) CD ( ) ; 30 40% IC CoO

2 2 1 CoO (PWLE: per wafer level exposed) Normalized CoO ($/GWLE) CoO Sensitivity (Impact to $/GWLE to input parameter) Throughput Throughput (WPH) (WPH) Litho Cell Cost Cost Mask Cost Mask Usage Product Yield w/ rework Litho Cell Reliability (MTBF) Product Yield NO Rework Normalized Input Variation Figure 66 Plot of Normalized Cost of Ownership as a Function of Several Normalized Input Variables 2 Cpwle = (Ce + Cl + Cf + Cc + Cr Qrw Nc ) / Ng + Cm / Nwm : Cpwle = Ce= ( ) Cl= Cf = Cc = ( ) Cr = Qrw= Nc = Tnet= = * Ng = (GWLE: good wafers levels exposed) = Tnet YL dt Y L = t= Cm = Nwm =

3 3 Ce ( 5 ) CoO Ce Tnet Cm Nwm Figure 66 CoO (Tnet) (Nwm) 45 nm Rayleigh R : λ R = k1 [1] NA λ NA nsinα 0 n α 0 k CD (DOF depth of focus) 1 DOF = k 3 n sin n =1 NA<0.8 DOF 2 λ sin ( sinα o ) 2 n [2] λ DOF k 2 [3] NA 2 (k2 k3) k 1 Ar (193nm) ArF, EUV(Extreme Ultraviolet) DOF [1] [3] (OAI: off-axis illumination) (PSM: phase shifting mask) (OPC: optical proximity correction) (RET: Resolution Enhancement Technique) ArF(193nm) RET NA Table 74 RET OPC RET 1 Burn Lin, The k3 coefficient in nonparaxial λ/na scaling equations for resolution, depth of focus, and immersion lithography, Journal of Microlithography, Microfabrication and Microsystems 1(1), 7 12, April 2002.

4 4 32 nm ArF 32 nm 2 EUV (ML2: Maskless Lithography) (NGL next-generation lithography) Table 74 Various Techniques for Achieving Desired CD Control and Overlay with Optical Projection Lithography MPU M1 contacted ½ pitch 210 nm 160 nm 120 nm 90 nm 65 nm 45 nm k 1 Range [A] Design rules Restrictions (cumulative) Masks (Optical proximity correction) (Gate and M1 layer mask type) (Contacts/vias layers mask type) Resist Tool Minor restriction Allow OPC and PSM, SRAF Minimum pitch, spacing and linewidth Rule-based OPC, MBOPC for gate, custom OPC for memory cells Model-based OPC (MBOPC) on critical layers, SRAF on gate layer cpsm and EPSM EPSM Pitch and orientation Litho friendly design rules Contact locations, library cells checked for OPC compatibility and printability Model-based OPC w /SRAF on critical layers, verification of entire corrected layout with simulation APSM, EPSM and hit EPSM Custom by layer type Features on grid?, Restricted feature set? Model-based OPC with vector simulation, SRAF, polarization corrections APSM, hit EPSM, dual dipole? APSM, EPSM, HiT PSM Model-based OPC with vector simulation, SRAF, polarization corrections, variation of OPC intensity by location in circuit?, magnification increase? APSM, hit EPSM, double exposure with 2 larger pitch Thickness <500 nm <400 nm <350 nm <280 nm <225 nm <160 nm Substrate ARC ARC, hard masks ARC, hard masks, top coats Etch (Illumination) (Dose control) (Process control (CD and overlay) Conventional, annular illumination Offsets from previous lots Selection based on aberrations, automated NA/sigma control Off-axis illumination Cross wafer dose adjustments Quadrupole Post development resist width reduction Custom illumination Automated process control with downloaded offsets Aberration monitoring Custom illumination, polarization optimization Dose adjustment across the wafer and along scan Custom illumination, polarization optimization Automated process control with downloaded offsets, metrology integrated in lithography cell MBOPC model based optical proximity correction cpsm complementary PSM APSM alternating PSM EPSM embedded PSM HiT high transmission ARC antireflection coating SRAF sub-resolution assist features Table 74 : [A]

5 5 10 Table 75 MPU ( ) k1 MEEF(mask error enhancement factor) nm 4 9 nm 14 nm nm 3.0 nm ArF OPC PSM CD (ESD: electrostatic discharge) RET 4 NA>0.9 NA> TE(Transverse Electric) 4 CD RET APC(automated process control) Table 74 CD DFM(design for manufacturing) DFM IC CMP CD EDA

6 6 DFM DFM (ROI) 450mm MPU CD CD LER(Line Edge Roughness) ArF 45 nm >1.44 CaF 2 (>1.56) EUV 32 nm 45 nm EUV 13.5 nm 13.5 nm EUV Table 75 ; EUV 13.5 nm LWR(Line Width Roughness) EUV (Longer Term) CD to to PFAS(perfluoroalkyl sulfonate)

7 7 LWR Difficult Challenges 32 nm Table 75 Optical masks with features for resolution enhancement and post-optical mask fabrication Cost control and return on investment Process control Immersion lithography EUV lithography Lithography Difficult Challenges Summary of Issues Registration, CD, and defect control for masks Equipment infrastructure (writers, inspection, metrology, cleaning, repair) for fabricating masks with sub-resolution assist features Understanding polarization effects at the mask and effects of mask topography on imaging and optimizing mask structures to compensate for these effects Eliminating formation of progressive defects and haze during exposure Determining optimal mask magnification ratio for <45 nm half pitch patterning with 193 nm radiation and developing methods, such as stitching, to compensate for the potential use of smaller exposure fields Development of defect free 1 templates Achieving constant/improved ratio of exposure related tool cost to throughput over time Cost-effective resolution enhanced optical masks and post-optical masks, and reducing data volume Sufficient lifetime for exposure tool technologies Resources for developing multiple technologies at the same time ROI for small volume products Stages, overlay systems and resist coating equipment development for wafers with 450 mm diameter Processes to control gate CDs to < 4 nm 3σ New and improved alignment and overlay control methods independent of technology option to <11 nm 3σ overlay error Controlling LER, CD changes induced by metrology, and defects < 50 nm in size Greater accuracy of resist simulation models Accuracy of OPC and OPC verification, especially in presence of polarization effects Control of and correction for flare in exposure tool, especially for EUV lithography Lithography friendly design and design for manufacturing (DFM) Control of defects caused in immersion environment, including bubbles and staining Resist chemistry compatibility with fluid or topcoat and development of topcoats Resists with index of refraction > 1.8 Fluid with refractive index > 1.65 meeting viscosity, absorption, and fluid recycling requirements Lens materials with refractive index >1.65 meeting absorption and birefringence requirements for lens designs Low defect mask blanks, including defect inspection with < 30 nm sensitivity and blank repair Source power > 115 W at intermediate focus, acceptable utility requirements through increased conversion efficiency and sufficient lifetime of collector optics and source components Resist with < 3 nm 3σ LWR, < 10 mj/cm 2 sensitivity and < 40 nm ½ pitch resolution Fabrication of optics with < 0.10 nm rms figure error and < 10% intrinsic flare Controlling optics contamination to achieve > five-year lifetime Protection of masks from defects without pellicles Mix and match with optical lithography

8 8 Table 75 Difficult Challenges < 32 nm Mask fabrication Metrology and defect inspection Cost control and return on investment Gate CD control improvements and process control Resist materials Lithography Difficult Challenges (continued) Summary of Issues Defect-free masks, especially for 1 masks for imprint and EUVL mask blanks free of printable defects Timeliness and capability of equipment infrastructure (writers, inspection, metrology, cleaning, repair), especially for 1 masks Mask process control methods and yield enhancement Protection of EUV masks and imprint templates from defects without pellicles Phase shifting masks for EUV Resolution and precision for critical dimension measurement down to 6 nm, including line width roughness metrology for 0.8 nm 3σ Metrology for achieving < 2.8 nm 3σ overlay error Defect inspection on patterned wafers for defects < 30 nm, especially for maskless lithography Die-to-database inspection of wafer patterns written with maskless lithography Achieving constant/improved ratio of exposure-related tool cost to throughput Development of cost-effective optical and post-optical masks Achieving ROI for industry with sufficient lifetimes for exposure tool technologies and ROI for small volume products Development of processes to control gate CD < 1.3 nm 3σ with < 1.5 nm 3σ line width roughness Development of new and improved alignment and overlay control methods independent of technology option to achieve < 2.8 nm 3σoverlay error, especially for imprint lithography Process control and design for low k 1 optical lithography Resist and antireflection coating materials composed of alternatives to PFAS compounds Limits of chemically amplified resist sensitivity for < 32 nm half pitch due to acid diffusion length Materials with improved dimensional and LWR control : (Table 76a b) (Table 77a b c) (Table 78a-f) MPU ( ) CD 10% MPU CD 10% 12% MPU CD LSI LER LWR LWR LWR IC MPU 2003

9 9 Table 76a b LWR Table 77a-c (NGL) NGL NGL EUV ( Table 78a b Table 78c d Table 78e f) EUV (UV-NIL) EUV EUV CD 4 1/16 EUV NGL CD ( / ) CIM (APC) Factory Integration

10 10 Table 76a Lithography Technology Requirements Near-term Years Year of Production DRAM ½ pitch (nm) (contacted) DRAM and Flash DRAM ½ pitch (nm) Flash ½ pitch (nm) (un-contacted poly) Contact in resist (nm) Contact after etch (nm) Overlay [A] (3 sigma) (nm) CD control (3 sigma) (nm) [B] MPU MPU/ASIC Metal 1 (M1) ½ pitch (nm) MPU gate in resist (nm) MPU physical gate length (nm) * Contact in resist (nm) Contact after etch (nm) Gate CD control (3 sigma) (nm) [B] ** MPU/ASIC Metal 1 (M1) ½ pitch (nm) Chip size (mm 2 ) Maximum exposure field height (mm) Maximum exposure field length (mm) Maximum field area printed by exposure tool (mm 2 ) Number of mask levels MPU Number of mask levels DRAM Wafer size (diameter, mm) *MPU OTRC ** 3 Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

11 11 Table 76b Lithography Technology Requirements Long-term Years Year of Production DRAM ½ pitch (nm) (contacted) DRAM and Flash DRAM ½ pitch (nm) Flash ½ pitch (nm) (un-contacted poly) Contact in resist (nm) Contact after etch (nm) Overlay [A] (3 sigma) (nm) CD control (3 sigma) (nm) [B] MPU MPU/ASIC Metal 1 (M1) ½ pitch (nm) MPU gate in resist (nm) MPU physical gate length (nm) * Contact in resist (nm) Contact after etch (nm) Gate CD control (3 sigma) (nm) [B] MPU/ASIC Metal 1 (M1) ½ pitch (nm) Chip size (mm 2 ) Maximum exposure field height (mm) Maximum exposure field length (mm) Maximum field area printed by exposure tool (mm 2 ) Number of mask levels MPU Number of mask levels DRAM Wafer size (diameter, mm) * MPU OTRC Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known Table 76a and b [A] Overlay (nm) Overlay X Y P1 ( ) P2 overlay O=P1-P2 O X Y 3 [B] CD control (nm) CD ( ) ( )

12 12 Table 77a Resist Requirements Near-term Years Year of Production DRAM ½ pitch (nm) (contacted) Flash ½ pitch (nm) (un-contacted poly) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU physical gate length (nm) [after etch] MPU gate in resist length (nm) Resist Characteristics * Resist meets requirements for gate resolution and gate CD control (nm, 3 sigma) ** Resist thickness (nm, single layer) *** PEB temperature sensitivity (nm/c) Backside particle density (particles/cm 2 ) Back surface particle diameter: lithography and measurement tools (nm) Defects in spin-coated resist films (#/cm 2 ) Minimum defect size in spin-coated resist films (nm) Defects in patterned resist films, gates, contacts, etc. (#/cm 2 ) Minimum defect size in patterned resist (nm) Low frequency line width roughness: (nm, 3 sigma) <8% of CD ***** Table 77b Resist Requirements Long-term Years Year of Production DRAM ½ pitch (nm) (contacted) Flash ½ pitch (nm) (un-contacted poly) MPU/ASIC Metal 1 (M1) ½ pitch (nm)(contacted) MPU physical gate length (nm) [after etch] MPU gate in resist length (nm) Resist Characteristics * Resist meets requirements for gate resolution and gate CD control (nm, 3 sigma) ** Resist thickness (nm, single layer) *** PEB temperature sensitivity (nm/c) Backside particle density (particles/cm 2 ) Back surface particle diameter: lithography and measurement tools (nm) Defects in spin-coated resist films (#/cm 2 ) Minimum defect size in spin-coated resist films (nm) Defects in patterned resist films, gates, contacts, etc. (#/cm 2) Minimum defect size in patterned resist (nm) Low frequency line width roughness: (nm, 3 sigma) <8% of CD ***** Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

13 13 Table 77a b : * ( ) ** *** 2.0:1 3.5:1. **** ***** LWR Lf 0.5 µm -1 1/(2*MPU ½ Pitch) 3σ : SEM 2 µim 4 nm : [A] [B] 90±2 [C] 130 [D] (PHOST: poly hydroxystyrene) [E] [F] <1000pptM [G] Metal < 5ppb [H] 2 (molecules/cm 2 sec) 193 nm <1e12 EUV <5e13 EPL [I] 2 Si (molecules/cm 2 sec) 193 nm <1e8 EUV <5e13 Table 77c Resist Sensitivities Exposure Technology Sensitivity 248 nm mj/ cm nm mj/ cm 2 Extreme Ultraviolet at 13.5 nm 5 15 mj/ cm 2 High Voltage Electron Beam ( kv) **** 5 10 µc/ cm 2 Low Voltage Electron Beam (1 2 kv) **** µc/ cm 2 ****

14 14 Table 78a Optical Mask Requirements Near-term Years Year of Production DRAM ½ pitch (nm) (contacted) DRAM/Flash CD control (3 sigma) (nm) MPU/ASIC Metal 1 (M1) ½ pitch (nm)(contacted) MPU gate in resist (nm) MPU physical gate length (nm) Gate CD control (3 sigma) (nm) [B] Overlay (3 sigma) (nm) Contact after etch (nm) Mask magnification [B] Mask nominal image size (nm) [C] Mask minimum primary feature size [D] Mask sub-resolution feature size (nm) opaque [E] Image placement (nm, multipoint) [F] CD uniformity allocation to mask (assumption) MEEF isolated lines, binary or attenuated phase shift mask [G] CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary or attenuated phase shift mask [H] * MEEF dense lines, binary or attenuated phase shift mask [G] CD uniformity (nm, 3 sigma) dense lines (DRAM half pitch), binary or attenuated phase shift mask [J] MEF contacts [G] CD uniformity (nm, 3 sigma), contact/vias [K] * Linearity (nm) [L] CD mean to target (nm) [M] Defect size (nm) [N] * Blank flatness (nm, peak-valley) [O] Data volume (GB) [P] Mask design grid (nm) [Q] Attenuated PSM transmission mean deviation from target (± % of target) [R] Attenuated PSM transmission uniformity (±% of target) [R] Attenuated PSM phase mean deviation from 180º (± degree) [S] Alternating PSM phase mean deviation from nominal phase angle target (± degree) [S] Alternating PSM phase uniformity (± degree) [T] Mask materials and substrates Absorber/attenuator on fused silica Pellicle for optical masks for exposure wavelengths down to 193 nm, including masks for 193 nm immersion. * 3 Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

15 15 Table 78b Optical Mask Requirements Long-term Years Year of Production DRAM ½ pitch (nm) (contacted) DRAM/Flash CD control (3 sigma) (nm) MPU/ASIC Metal 1 (M1) ½ pitch (nm)(contacted) MPU gate in resist (nm) MPU physical gate length (nm) Gate CD control (3 sigma) (nm) [B] Overlay (3 sigma) (nm) Contact after etch (nm) Mask magnification [B] Mask nominal image size (nm) [C] Mask minimum primary feature size [D] Mask sub-resolution feature size (nm) opaque [E] Image placement (nm, multipoint) [F] CD uniformity allocation to mask (assumption) MEEF isolated lines, binary or attenuated phase shift mask [G] CD uniformity (nm, 3 sigma) isolated lines (MPU gates), binary or attenuated phase shift mask [H] MEEF dense lines, binary or attenuated phase shift mask [G] CD uniformity (nm, 3 sigma) dense lines (DRAM half pitch), binary or attenuated phase shift mask [J] MEF contacts [G] CD uniformity (nm, 3 sigma), contact/vias [K] Linearity (nm) [L] CD mean to target (nm) [M] Defect size (nm) [N] * Blank flatness (nm, peak-valley) [O] Data volume (GB) [P] Mask design grid (nm) [Q] Attenuated PSM transmission mean deviation from target (± % of target) [R] Attenuated PSM transmission uniformity (± % of target) [R] Attenuated PSM phase mean deviation from 180º (± degree) [S] Alternating PSM phase mean deviation from nominal phase angle target (± degree) [S] Alternating PSM phase uniformity (± degree) [T] Mask materials and substrates Absorber/attenuator on fused silica Pellicle for optical masks for exposure wavelengths down to 193 nm, including masks for 193 nm immersion. Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

16 16 Table 78a and b : [A] Wafer Minimum Line Size ( ) [B] Magnification [C] Mask Nominal Image Size [D] Mask Minimum Primary Feature Size OPC [E] Mask Sub-Resolution Feature Size [F] Image Placement (X Y) [G] MEEF(Mask Error Factor) MEEF 1 [H] CD Uniformity 3σ X Y [I] CD Uniformity 3σ X Y [J] CD Uniformity 3σ X Y [K] CD Uniformity 3σ [L] Linearity 3/2 [M] CD Mean to Target ( - )/ [N] Defect Size 10% [O] Blank Flatness mm 140 mm nm [P] Data Volume [Q] Mask Design Grid [R] Transmission % [S] Phase 2 [T] Alt PSM

17 17 Table 78c EUVL Mask Requirements Near-term Years Year of Production DRAM ½ pitch (nm) (contacted) Flash ½ pitch (nm) (un-contacted poly) DRAM/Flash CD control (3 sigma) (nm) MPU/ASIC Metal 1 (M1) ½ pitch (nm)(contacted) MPU gate in resist (nm) MPU physical gate length (nm) Gate CD control (3 sigma) (nm) [B] Overlay Contact after etch (nm) Generic Mask Requirements Mask magnification [B] Mask nominal image size (nm) [C] Mask minimum primary feature size [D] Image placement (nm, multipoint) [E] CD uniformity (nm, 3 sigma) [F] Isolated lines (MPU gates) Dense lines DRAM (half pitch) Contact/vias Linearity (nm) [G] CD mean to target (nm) [H] Defect size (nm) [I] Data volume (GB) [J] Mask design grid (nm) [K] EUVL-specific Mask Requirements Substrate defect size (nm) [L] Mean peak reflectivity 65% 66% 66% 66% 67% 67% Peak reflectivity uniformity (% 3 sigma absolute) 0.69% 0.58% 0.47% 0.42% 0.37% 0.33% Reflected centroid wavelength uniformity (nm 3 sigma) [M] Absorber sidewall angle tolerance (± degrees) [P] Absorber LER (3 sigma nm) [N] Mask substrate flatness (nm peak-to-valley) [O] Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

18 18 Table 78d EUVL Mask Requirements Long-term Years Year of Production DRAM ½ pitch (nm) (contacted) Flash ½ pitch (nm) (un-contacted poly) DRAM/Flash CD control (3 sigma) (nm) MPU/ASIC Metal 1 (M1) ½ pitch (nm)(contacted) MPU gate in resist (nm) MPU physical gate length (nm) Gate CD control (3 sigma) (nm) [B] Overlay Contact after etch (nm) Generic Mask Requirements Mask magnification [B] Mask nominal image size (nm) [C] Mask minimum primary feature size [D] Image placement (nm, multipoint) [E] CD Uniformity (nm, 3 sigma) [F] Isolated lines (MPU gates) Dense lines DRAM (half pitch) Contact/vias Linearity (nm) [G] CD mean to target (nm) [H] Defect size (nm) [I] Data volume (GB) [J] Mask design grid (nm) [K] EUVL-specific Mask Requirements Substrate defect size (nm) [L] Mean peak reflectivity 67% 67% 67% 67% 67% 67% 67% Peak reflectivity uniformity (% 3 sigma absolute) 0.29% 0.26% 0.23% 0.21% 0.19% 0.17% 0.15% Reflected centroid wavelength uniformity (nm 3 sigma) [M] Absorber sidewall angle tolerance (± degrees) [P] Absorber LER (3 sigma nm) [N] Mask substrate flatness (nm peak-to-valley) [O] Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known Table 78c d : EUVL [A] Wafer Minimum Line Size ( ) [B] Magnification [C] Mask Nominal Image Size N [D] Mask Minimum Primary Feature Size OPC [E] Image Placement (X Y) [F] CD Uniformity 3σ X Y : ( ) ( ) [G] Linearity 3/2

19 19 [H] CD Mean to Target ( - )/ [I] Defect Size 10% [J] Data Volume 1 [K] Mask Design Grid [L] Substrate Defect Size [M] [N] Line edge roughness (LER) 3σ [O] Mask Substrate Flatness 5 mm nm peak-to-valley [P]

20 20 Table 78e Imprint Template Requirements Near-term Years Year of Production DRAM ½ pitch (nm) (contacted) Flash ½ pitch (nm) (un-contacted poly) DRAM/Flash CD control (3 sigma) (nm) MPU/ASIC Metal 1 (M1) ½ Pitch (nm)(contacted) MPU gate in resist (nm) MPU physical gate length (nm) Overlay (3 sigma) (nm) Gate CD control (3 sigma) (nm) Contact after etch (nm) Generic Mask Requirements Magnification [B] Mask nominal image size (nm) [C] Image placement (nm, multipoint) [D] CD Uniformity (nm, 3 sigma) [E] Isolated lines (MPU gates) Dense lines DRAM/Flash (half pitch) Contact/vias Linearity (nm) [F] CD mean to target (nm) [G] Data volume (GB) [H] Mask design grid (nm) [I] UV-NIL-specific Mask Requirements Defect size impacting CD (nm) x, y [J] Defect size impacting CD (nm) z [K] Mask substrate flatness (nm peak-to-valley) [L] Trench depth, mean (nm) [M] Etch depth uniformity (nm) [N] Trench wall angle (degrees) [O] Trench width roughness (nm, 3 sigma) [P] Corner radius, bottom of feature (nm) [Q] Corner radius, top of feature (nm) [R] Trench bottom surface roughness (nm, 3 sigma) [S] Template absorption [T] <2% <2% <2% <2% <2% <2% Near surface defect (nm) [U] Defect size, patterned template (nm) [V] Defect density (#/cm 2 ) [W] Dual Damascene overlay: metal/via (nm, 3 sigma) [X] Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

21 21 Table 78f Imprint Template Requirements Long-term Years Year of Production DRAM ½ pitch (nm) (contacted) Flash ½ pitch (nm) (un-contacted poly) DRAM/Flash CD control (3 sigma) (nm) MPU/ASIC Metal 1 (M1) ½ pitch (nm)(contacted) MPU gate in resist (nm) MPU physical gate length (nm) Overlay (3 sigma) (nm) Gate CD control (3 sigma) (nm) Contact after etch (nm) Generic Mask Requirements Magnification [B] Mask nominal image size (nm) [C] Image placement (nm, multipoint) [D] CD Uniformity (nm, 3 sigma) [E] Isolated lines (MPU gates) Dense lines DRAM/Flash (half pitch) Contact/vias Linearity (nm) [F] CD mean to target (nm) [G] Data volume (GB) [H] Mask design grid (nm) [I] UV-NIL-specific Mask Requirements Defect size impacting CD (nm) x, y [J] Defect size impacting CD (nm) z [K] Mask substrate flatness (nm peak-to-valley) [L] Trench depth, mean (nm) [M] Etch depth uniformity (nm) [N] Trench wall angle (degrees) [O] Trench width roughness (nm, 3 sigma) [P] Corner radius, bottom of feature (nm) [Q] Corner radius, top of feature (nm) [R] Trench bottom surface roughness (nm, 3 sigma) [S] Template absorption [T] <2% <2% <2% <2% <2% <2% <2% Near surface defect (nm) [U] Defect size, patterned template (nm) [V] Defect density (#/cm 2 ) [W] Dual Damascene overlay: metal/via (nm, 3 sigma) [X] Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

22 22 Table 78e f : [A] Wafer Minimum Feature Size ( ) [B] Magnification N:1 [C] Mask Nominal Image Size [D] (X or Y) [E] CD Uniformity 3σ X Y : sqrt ( ) sqrt ( ) [F] Linearity 3 [G] CD Mean to Target ( - )/ [H] [I] [J] Defect Size (nm) x, y 10% [K] Defect Size (nm) z 10% [L] 6 110mm (nm peak-to-valley) [M] Trench depth mean 2 1 MPU/ASIC [N] Trench depth uniformity in nm 5% [O] Trench wall angle in degrees 5 10: [P] Trench width roughness (nm, 3 sigma) LWR [Q] Corner radius, bottom of feature S-FIL/R ( ) CD (CD 12.5%) S-FIL ( ) [R] Corner radius, top of feature CD S-FIL ( ) (CD 3%) S-FIL/R ( ) [S] [T] 6.3 mm 365 nm (%) [U] 200nm [V] Defect size, patterned template (nm) [W] 1cm -2 [X] 3D figure 67 ArF DRAM 65 nm EUV ML2 45 nm 32 nm ArF(193 nm) KrF(248 nm) 157nm F 2 32 nm 2 2 2

23 23 DRAM 32 nm 2 DRAM 45 nm EUV EUV 32 nm 22 nm (ASIC) ML2 1 DRAM 16 nm ( ) 1 2 DRAM32 nm

24 DRAM 1/2 Pitch 65nm 45nm 32nm 22nm 16nm DRAM Half-pitch nm 193 nm immersion with water Flash Half-pitch nm immersion with water 193 nm immersion with other fluids EUV, ML2 Narrow options 32 EUV 193 nm immersion with other fluids and lens material Innovative 193 nm immersion with water Imprint, ML2 Narrow options i 22 EUV Innovative 193 nm immersion Imprint, ML2, innovative technology Narrow options 16 Innovative technology Innovative EUV, imprint, ML2 Narrow options Research Required Development Underway Qualification/Pre-Production Continuous Improvement This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution. Notes: RET and lithography friendly design rules will be used with all optical lithography solutions, including with immersion; therefore, they are not explicitly noted. Figure 67 Lithography Exposure Tool Potential Solutions Lithography ESH Factory Integration Yield Enhancement Metrology Modeling and Simulation Device and Circuit performance Emerging Research Devices and Materials (ESH) Perfluoroalkyl sulfonates(pfas) ESH EUV EUV EUV (wall-plug) ( )

25 25 (FACTORY INTEGRATION) ( ) SECS/GEM (OCR) CD (Litho stack) (Integrated) / (Dose) (Focus) (Tilt) (YIELD ENHANCEMENT) ML2 Die-to-Database DFM (AMC) AMC Yield Enhancement EUV (METROLOGY) CD 20% CD 3D CD CD-SEM SPM( )

26 26 LWR LWR ( ) LWR LWR OPC (MODELING AND SIMULATION) ( ) (OAI) OPC EUV ML2 NA0.85 LER

27 27 / CD CD-SEM LWR LER (LER) (LWR) / OPC Modeling Simulation ITWG CD LWR PIDS FEP CD CD TWG +/-12% CD 2 CD

28 28