? FPGA FPGA FPGA : : :

? ( ) (FFT) ( ) (Localization)

? : 0. 1 2 3 0. 4 5 6 7 3 8 6 1 5 4 9 2 0. 0 5 6 0 8 8 ( )

? : LU Ax = b LU : Ax = 211 410 221 x 1 x 2 x 3 = 1 0 0 21 1 2 1 0 0 1 2 x = LUx = b 1 31 00 4 : y Ux Ly = b Ux = y (Matrix) Local ( )

? : F = 1 1 1 1 1 W W 2 W N 1 1 W 2 W 4 W 2N 2......... 1 W N 1 W 2N 2 W (N 1)(N 1) O(n 2 ) O(n log n), W n = 1

? : : CPU : L, C, R OP,.. :

? Problem Structure Operation Algorithm Hardware Topology Dynamics : : CPU :

? CPU Memory Instruction/Data Bus : : (Field Programmable Gate Array) ( )

FPGA? FPGA FPGA FPGA FPGA

FPGA : CMOS CMOS MOS A A A A NAND(A,B) B NOR(A,B) B Inverter NAND NOR

PLA X FPGA PLA (Programmable Logic Arrays) AND OR A B C D X=AB+ACD

FPGA FPGA LUT(Look Up Table) A B LUT (SRAM) NAND(A,B) AB 1 A B AB AB 1 1 OUT CMOS NAND AB 0 LUT

FPGA FPGA Logic Cell[LUT( ), FF( )] Matrix Logic Cell Logic Cell Logic Cell Logic Cell SW Logic Cell Logic Cell Logic Cell SW SW Logic Cell Logic Cell Logic Cell Logic Cell SW

FPGA 1. (Hardware Description Language) 2. 3. 4. FPGA FPGA 5. FPGA

FPGA HDL (Hardware Description Language) HDL: Verilog-HDL, VHDL, SFL : 4 Verilog module count(out, ck); output [3:0] out; input ck; reg [3:0] q; always @(posedge ck) begin q <= q+1; end assign out = q; endmodule

FPGA HDL (VCS ) module testcount; wire [3:0] out; reg ck; initial begin ck <= 0; #200 $finish; end always #10 begin ck <= ck; end count inst0 (out, ck); endmodule ck out[3] out[2] out[1] out[0]

FPGA (FPGA Express ) FPGA FPGA JTAG ROM

FPGA PCI PCI FPGA CPU Memory PCI Bridge FPGA board

FPGA FPGA 1 1 ( )

FPGA 1 FPGA CPU FPGA CPU

FPGA Web

? FPGA

integers binary codes Gray codes 0 000 000 1 001 001 2 010 011 3 011 010 4 100 110 5 101 111 6 110 101 7 111 100

1 1 2

x B=0.0010... y =0.... B x G=0.0011... y G= 0. 100... bit 3 bit 2 bit 1 bit 3 bit 2 bit 1 0 1 bit 0 bit 0 0 1/4 1/2 3/4 1 Binary code 2 0 1/4 1/2 3/4 1 Gray code

2 2 1 1 0 0 + 0 0 1 1 0 1 1 1 1 1 1 0 1 + 0 0 1 1 1 0 0 0 0 ( )

a b G G 0.11111 0.01111 Gray Code Adder.1000 c G 0.1 [0.1, 0.2]

2 1 2

Why Gray codes? 1/2 [ 1 X = 2 ε 1, 1 ] 2 + ε 2, ε 1,ε 2 > 0 X B=0. X G= 0. 100 bit 3 bit 2 bit 1 bit 3 bit 2 bit 1 0 1 bit 0 bit 0 0 1/4 1/2 3/4 1 Binary code 1 0 1/4 1/2 3/4 1 Gray code 1

x G x G X = [X, X] = [x 1, x + 1] 2 n x x : (integer), n x : (integer) x = 0. G 1 2 0 1 left 0 1/4 1/2 3/4 1 right center x G= 0.0 x G= 0. 1 x G= 0.1 1 2 1 2 1 2 0 1/4 1/2 3/4 1 0 1/4 1/2 3/4 1 0 1/4 1/2 3/4 1

a G b G = c G a G A, b G B c G C A B C A B A B C a G, b G = A, B = A B C = c G

d, d ( ) d = 2 n c A B C ( ) d = 2 n c C A B C d2 -n c A B d2 -n c A B A B, C d, d C A B conditions c G d d d 1, left 1 := P c d := 2d d := 2(d 1) d 1, right 1 := P c d := 2(d 1) d := 2d d 1 / 2 d 1 / 2, center 2 := 1, 0 d := 2(d 1 / 2 ) d := 2(d 1 / 2 ) P c = i b 1 j= c j (i b = 1 ) C

? FPGA

: : xy = 1 y = 1/x : x 2 + y 2 2 = 0, xy 1 = 0 x 4 + 2x 2 1 = 0, x 3 2x + y = 0

Ax = y x y y x a 11 a 12 a 1n a 21 a 22 a 2n.... a n1 a n2 a nn x 1 x 2. x n = y 1 y 2. y n LU L 1 u 11 u 12 u 1n 0 a 22 u 2n........ 0 0 u nn x 1 x 2. x n = l 11 0 0 l 21 l 22 0........ l n1 l n2 l nn y 1 y 2. y n x y y x

y(t) = t 0 g(t τ)x(τ)dτ x(t) y(t) y(t) x(t) Y(s) = G(s)X(s), G(s) 1 Y(s) = X(s) X(s) Y(s) Y(s) X(s)?

F(s) = = 0 0 f (t)e st dt f (t)e at e jωt dt f (t) e at (s = a + jω) :?

f (t) = L 1 [F(s)](t) = 1 2πj a+j a j F(s)e st ds s:, f (t):, F(s): = Bromwich ε FFT

1/ s f N (t) 1.5 1.0 0.5 FFT-Based square wave f N (t) 2.0 1.5 1.0 0.5 FFT-Based 1/ πt 0.0 0.0-0.5 0.0 0.5 1.0 1.5 2.0 F(s) = t 1 s(1 + e 0.1s ) -0.5 0.0 0.5 1.0 1.5 2.0 F(s) = 1 s t

F(s) G(s) t F(s) G(s) FFT-Based g N(hn) T T -1 inversion ^ N f (hn) T s T 1 t

s f (t) = L 1 [F(s)] = L 1 [s i F(s) s i ] = di dt i L 1 [ F(s) s i ] = s i + t i s domain t domain Conventional method F(s) FFT-Based inversion f (hn) N Proposed method F(s) 1 si i-th integral G(s) FFT-Based inversion g N (hn) i d dt i-th differential i ^ N f (hn)

1/ s f N (t) 1.5 1.0 0.5 FFT-Based square wave Proposed (i=4) f N (t) 2.0 1.5 1.0 0.5 FFT-Based 1/ πt Proposed (i=4) 0.0 0.0-0.5 0.0 0.5 1.0 1.5 2.0 F(s) = t 1 s(1 + e 0.1s ) -0.5 0.0 0.5 1.0 1.5 2.0 F(s) = 1 s t

? FPGA

(SFQ)

A A B B A B A B A B

: z = f (w 1 x 1 + w 2 x 2 + w n x n θ) x x x 1 2 w w w 3 3 θ x n 2 w n 1 z 1 0 f

(CML) A OUT OUT B A B CML ExOR

(Exp ) O1 O2 X1 X2 Y1 Y2

: (TDM, FDM, CDM, SDM,...) : FPGA V(t) A B C D 0 90 V(t) 180 270 A B C D

? :? A NOT B A B AND C A B OR C NOT A B 0 1 1 0 AND A B C 0 0 0 0 1 0 1 0 0 1 1 1 OR A B C 0 0 0 0 1 1 1 0 1 1 1 1

? :? CMOS : : IN OUT IN / OUT OUT / IN CMOS inverter Pass-transistor

? a + b = c. a b, c = a + b b c, a = c b

2 1 2 1 1 A B A B 0 0 1 1 A B 0 1 1 0 1 1 2 2 1 A B C A B C 0 0 0 0 1 1 1 0 1 1 1 0 A B C 0 0 1 0 1 0 1 0 0 1 1 1

AND A B AND C Z (a) (b) (c) Input Input Output Input Input Output Input Input Output A B C A C B B C A Z Z Z Z Z Z Z Z Z Z 0 0 Z 0 Z Z 0 Z Z 1 Z Z 1 1 Z 1 1 0 Z 0 0 Z Z 0 Z Z 0 0 0 0 0 Z 0 0 Z 0 1 0 0 1-0 1-1 Z Z 1 Z Z 1 Z Z 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1

2 : X=1 X=0 (X,X)=(1,0) (X,X)=(0,1). : (X,X) = (0,0). A B A B : IN / OUT OUT / IN

Expression of the unfixed bit Two-way circuit 0, 1, Z OUT OUT open pull down (V) OUT OUT 0 0 5 1 5 0 Z 0 0

ExOR A =0 B C A=1 B C A, B and C Gate control Signal flow B B B B A A BBCC A A A A C C C C B C C ExOR B (a) (b) Input Input Output A A B B C C 0 1 0 1 0 1 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1

AND A = 1 B C A = 0 A C C=1, A, B A A B B C C A A B B C AND C

A, B, C, S and C +. A, C, S, B. C+ C+ carry out a n b n FA(n) s n+1 sn c2 A A B B Reversible ExOR C C Reversible ExOR carry in sum S S a 1 b1 a 0 b 0 FA(1) c 1 FA(0) c 0 = 0 s 1 s 0 n-bit

2 2bit c 0 = a 0 b 0, c 1 = a 1 b 0 a 0 b 1, c 2 = a 1 b 1 (a 1 b 0 a 0 b 1 ), c 3 = a 1 b 1 a 1 b 0 a 0 b 1. A a 1 a 0 B b 1 b 0 Two-way AND a 1 b 1 a 0 b 1 a 1 b 0 a 0 b 0 Reversible ExOR 2 2 bit Reversible ExOR buffer C c 3 c 2 c 1 c 0 carry out carry out augend FA sum augend HA sum carry in addend addend a 2 b 2 FA a 1 b 2 FA HA a 2 b 1 a 0 b 2 a 0 b 1 a 0 b 0 a 1 b HA 1 FA a 2 b 0 HA a 1 b 0 c 5 c 4 c 3 c 2 c 1 c 0 3 3 bit