main.dvi

CAD 2001 12

1 1, Verilog-HDL, Verilog-HDL. Verilog-HDL,, FPGA,, HDL,. 1.1, 1. (a) (b) (c) FPGA (d). 2. 10,, Verilog-HDL, FPGA,. 1.2,,,, html. % netscape ref0177/html/index.html.,, View Encoding Japanese (Auto-Detect).

3 2 Ξ 2,. ± Π, % UNIX. %,. 2.1 FPGA, Verilog-HDL RTL, FPGA, Synopsys FPGA Compiler II( FCII ). FCII Verilog-HDL RTL( ), FPGA,, FPGA. FCII, circuit, circuit.edf EDIF, FPGA, circuit.acf 2. FPGA, FPGA ALTERA MAX+PLUSII(, MPII). MPII, FCII.edf.acf, FPGA.,.acf FPGA SRAM. FPGA, sof, ttf, pof. MPII, SRAM. acf FCII, MPII FPGA. 2.2 Verilog-HDL 1. Verilog., Verilog. netscape,. 2. verilog Verilog-XL. % verilog roulettesim.v roulette.v.

4 2 0: xxxxxx 10: 000001 30: 000010 40990: 000100 81950: 001000 122910: 010000 163870: 100000 Verilog,7 LED. LED 1. roulette.v module roulette(out,clk,rst); input CLK,RST; output [5:0] out; reg [5:0] out; reg [10:0] divide; // 11, 2 11 (2048 ). always @(posedge CLK or negedge RST) begin if(!rst) begin out<=1;divide<=0; end else begin if(divide==0)// 2048,. begin out[0]<=out[5]; out[1]<=out[0]; out[2]<=out[1]; out[3]<=out[2]; out[4]<=out[3]; out[5]<=out[4]; end divide<=divide+1; // 1. end end endmodule

2.3. FPGA Compiler II 5 roulettesim.v( ) timescale 1ns/100ps // 1ns, 100ps. module roulettesim; reg CLK,RST; wire [5:0] out; roulette I0(.out(out),.CLK(CLK),.RST(RST)); initial begin CLK=0;RST=1; #10 RST=0;// 10ns. #10 RST=1; #400000 $finish;//, 400usec end always #10 //, 20ns CLK= CLK; initial $monitor("%d: ",$time,"%b",out); initial begin $dumpfile("roulette.vcd"); //. $dumpvars;//. end endmodule 3. SimWave,.. % wd roulette.vcd #, wd, wd -inputformat vcd alias. 2.3 FPGA Compiler II % fc2 1. FPGA Compiler II.

6 2 2.,, Do not show this dialog again, Cancel. 3. File New Project,.,,, module., Create., (Name ) roulette.

2.3. FPGA Compiler II 7 4. Identify Sources,., roulette.v.,, Ctrl.,, Remove.. Design Sources, WORK +Add sources in WORK, Identify Sources. 5.,,. (roulette.v), module (roulette). 6. module ( roulette ), Create Implementation.

8 2 device., ± Vendor Altera Device EPF10K40RC208 Family FLEX10K Speed Grade 4 Π Ξ OK. 7. Chips (roulette), (roulette-optimized). 8. Chips module roulette, Edit Constraints. Ports, Pad Loc,,., Edit Constraints ( )., Windows., Do you wish to save the changes you made int the Constraint Editor, Yes.

2.3. FPGA Compiler II 9 Pad Loc out5 206 out4 205 out3 204 out2 203 out1 202 out0 200 CLK 183 RST 180 9., roulette-optimized.?, Edit Contstraints,. 10.,,.. ffl roulette, Optimize Chip. ffl roulette-optimized, Update Chip., roulette-optimized..? Optimize Chip Update Chip?

10 2 11.,, roulette-optimized, View Results. Edit Constraints, Ports, Edit Constraints., Pad Loc, Edit Contstraints, View Schematic,., Optimize Chip Update Chip. 12. Optimized, Export Netlist. EDIF,. Output Format Verilog, Verilog.. Verilog netlist Verilog MAX+plusII 13., FPGA CompilerII Optimized, Update Chip. 2.4 ( ) FPGA CompilerII, Verilog-HDL.,. % verilog roulettesim.v roulette/roulette.v, Warining,..,.,.

2.5. MAX+plusII FPGA 11 2.5 MAX+plusII FPGA MAX+PlusII, FPGA Compiler II, GUI. 2.5.1 GUI % max2win Ξ,10 Page Down ± Π., ± Π Ξ Yes, 1. MAX+plusII. 2.,.. 3. File Project Name, FPGA CompilerII ( ).edf., roulette/roulette.edf. 4. MAX+plus II Compiler,.

12 2 MAX+PLUSII 10.1,,. (project).. 5. Processing Fitter Setting. 6. ± Π Ξ, Use Quartus Fitter for FLEX 10K and ACEX 1K Devices. Start,. 2.6 1. MAX+plusII Programmer., Programming Hardware is not installed, OK.

2.7. 13 2. Options Hardware Setup, Hardware Type MasterBlaster(COM). 3. Programmer Configure.,.. 2.7. HDL testfixture,, verilog. % verilog roulettesim.v roulette.v HDL ( ) FPGA CompilerII export netlist verilog

14 2 % verilog roulettesim.v roulette/roulette.v.v FPGA /, warning. 2.8 % verilog -c circuit.v Verilog 1. Verilog, verilog. 2., FPGA Compiler II Optimized, Update Chip., Verilog, MAX+plusII.

15 3 FPGA 3.1, (http://www.mms.co.jp/) Power Medusa MU200-EA40.. ON ON ON ON ON ON OFF ON ON LED-A LED-B LED-C LED-D LED LED-E LED-F LED-G LED-H / / EPF10K 40RC208-4 4 RST ON ON A B C D E F G H SW19 SW23 SW27 SW31 SW35 SW20 SW24 SW28 SW32 SW36 SW21 SW25 SW29 SW33 SW37 SW22 SW26 SW30 SW34 SW38 0 7 LED 3.1: FPGA 3.2, LED( ). FPGA Compiler II PAD Loc,.

16 3 FPGA 183 CLK 180 RST 86 SW19 89 SW20 93 SW21 94 SW22 85 SW23 88 SW24 92 SW25 75 SW26 83 SW27 87 SW28 90 SW29 74 SW30 65 SW31 68 SW32 70 SW33 73 SW34 64 SW35 67 SW36 69 SW37 71 SW38 LED 103 LED-A 102 LED-B 101 LED-C 100 LED-D 99 LED-E 97 LED-F 96 LED-G 95 LED-H 7 A 208 h (7) 207 g (6) 206 f (5) 205 e (4) 204 d (3) 203 c (2) 202 b (1) 200 a (0) 7 B 199 h (7) 198 g (6) 197 f (5) 196 e (4) 195 d (3) 193 c (2) 192 b (1) 191 a (0) 7 C 190 h (7) 189 g (6) 187 f (5) 179 e (4) 177 d (3) 176 c (2) 175 b (1) 174 a (0) 7 D 173 h (7) 172 g (6) 170 f (5) 169 e (4) 168 d (3) 167 c (2) 166 b (1) 164 a (0) 7 E 163 h (7) 162 g (6) 161 f (5) 160 e (4) 159 d (3) 158 c (2) 157 b (1) 150 a (0) 7 F 149 h (7) 148 g (6) 147 f (5) 144 e (4) 143 d (3) 142 c (2) 141 b (1) 136 a (0) 7 G 139 h (7) 134 g (6) 133 f (5) 132 e (4) 131 d (3) 128 c (2) 127 b (1) 122 a (0) 7 H 121 h (7) 120 g (6) 119 f (5) 116 e (4) 115 d (3) 112 c (2) 111 b (1) 104 a (0) 3.3 7 LED 7 LED FPGA. 1 LED. LED 3.2.

3.4. 17 a e f d g c b h 3.2: 7 LED 3.4 FPGA., 20MHz 2 ( ).,4., 1.25MHz. 3.5 ( ON/OFF ),.,, 4 (1.25MHz ). 1, 0.. 3.3. 3.6 1.,, ON. 2. 1, 0.

18 3 FPGA 7 8 9 + SW19 SW23 SW27 SW31 SW35 86 85 83 65 4 5 6 - SW20 SW24 SW28 SW32 SW36 89 88 87 68 1 2 3 = SW21 SW25 SW29 SW33 SW37 93 92 90 70 10 FPGA 0 CE SW22 SW26 SW30 SW34 SW38 94 73 10 10 FPGA 10 FPGA 9 83 2 92 8 85 1 93 7 86 0 94 6 87 + 65 5 88 68 4 89 = 70 3 90 CE 73 3.3: 10

19 4, 3 (binshifttop, enzantop, calctop).. fc2 CLK CE.

20 4 binshifttop push9 83 push8 85 push7 86 push6 87 push5 88 push4 89 push3 90 push2 92 push1 93 push0 94 ledl6 189 ledl5 187 ledl4 179 ledl3 177 ledl2 176 ledl1 175 ledl0 174 ledh6 198 ledh5 197 ledh4 196 ledh3 195 ledh2 193 ledh1 192 ledh0 191 CLK 183 CE 73 RST 180 enzantop push9 83 push8 85 push7 86 push6 87 push5 88 push4 89 push3 90 push2 92 push1 93 push0 94 plus 65 equal 70 ledl6 189 ledl5 187 ledl4 179 ledl3 177 ledl2 176 ledl1 175 ledl0 174 ledh6 198 ledh5 197 ledh4 196 ledh3 195 ledh2 193 ledh1 192 ledh0 191 CLK 183 CE 73 RST 180 calctop push9 83 push8 85 push7 86 push6 87 push5 88 push4 89 push3 90 push2 92 push1 93 push0 94 plus 65 minus 68 equal 70 sign 207 overflow 103 ledl6 189 ledl5 187 ledl4 179 ledl3 177 ledl2 176 ledl1 175 ledl0 174 ledh6 198 ledh5 197 ledh4 196 ledh3 195 ledh2 193 ledh1 192 ledh0 191 CLK 183 CE 73 RST 180