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2 PLD 10M M 100k 10k PLA EEPROM SPLD FPGA CPLD SRAM FPGA

3 FPGA(Field Programmable Gate Array) LUT F.F LUT, SRAM IOB

4 FPGA-SRAM PLD(Programmable Logic Device) CPLD(Complex PLD) FPGA(Field Programmable Gate Array) LUT EEPROM SRAM CMOS

5 Xilinx Virtex II LUT LUT Carry Carry D Q D Q Slice X 2 CLB (Configurable Logic Block) Global Clock MUX DCM IOB Slice 10CLB 3Mbit Configurable Logic Programmable IOs RAM Multiplier

6 Altera Stratix II DSP Blocks PLL Mega RAM Blocks M4K RAM Blocks M512 RAM Blocks LABLogic Array Block 4LUTF.F. LE 10

7 SoPD (System on Programmable Device) DCM Xilinx Virtex-II Pro Rocket I/O, Multi-Gigabit Transceiver Power-PC Multiplier Block RAM CLBs FPGA

8 FPGA/CPLD XilinxVirtexAlteraAPEXStratix System on Programmable Device DLLCPUDSP,IP XilinxVirtex Pro (Power PC), AlteraExcalibur (ARM) IP Virtex-4 XilinxSpartan, AlteraCyclone

9 FPGAXilinx LUT 350nm XC4000 XC4085KLA V 250nm XC4000 XC40250KV V 220nm Virtex XCV V 180nm Virtex-E XCV2000E V 150nm Virtex-II XC2V800O V 130nm Virtex-II Pro XC2VP V 90nm Virtex-4 XC4VLX V 65nm Virtex-5 XC5VLX V

10 Virtex II ProCPURocket I/O DSPBRAM LX: EX:DSP FX:CPUI/O LX/EXVirtex II Pro Virtex-4 LX Virtex-4 SX Virtex-4 FX

11 XilinxSpartan(Spartan3E) 90nm 10I/ORAM DLL ASICSpartan Altera Cyclone II

12 LSI A B C D CPU for i=0; i<k; i++ X[i]=X[i+j]... CPU

13 (90 CPU50 (20MHz GH FPGA

14 Splash-2 () String matching, Image processing, DNA matching, Cray-II330 VHDL, Parallel C Annapolis Micro Systems(WILDFIRE)

15 RM-IV () FPGA mem mem mem mem FPIC mem mem mem mem mem mem mem mem Interface mem mem mem mem

16 RASH 61 2 clock lines PCI bus I/F A large SRAM DRAM daughter board FPGA Altera FLEX10K100A (62k-158kGate) StratixVirtex-Pro

17 DSP) IEEE 100MHz200MHzGH CPU2040 FPGA1670 CPU CRAY-XD1, RASC, SRC-6 BEE2, PROGRAPE-3, RAPLACE, ReCSiP FPGA

18 CRAY-XD1 AMD Opteron 2FPGAVirtex II Pro)1 61 Rapid Array Rocket I/OFPGA HDL

19 SGI RASC SGINUMA Altix Virtex II XC2V6000Virtex NUMAlink4 2

20 BEE2 (Berkeley Emulation Engine 2) 5 Virtex II FPGA 20 banks DDR2-400 memorys 18 10Gbps links Ethernet, USB RAMP1RAMP Blue

21 BEE2FPGA

22 PROGRAPE-3

23 FCCM,FPL,FPT

24 DSP FPGA 200MHz FPGA670 GHzCPU ( CPU 10 FPGA CPU

25 Virtex-4 XC4VLX200 ( Block RAM(64Kbit) (4) Coregen

26 Virtex-4 XC4VLX200 ( Block RAM(64Kbit) (4)

27 IEEE CPU PC FPGA XilinxFPGA

28 PCFPGA HDL FORTRANC

29 BLAS, MATLAB, SBML C BDL, Handel-C, Bach-C Bach-C

30 FPGA Block RAM

31 LUT Virtex-4 SDRAM BEE2

32 Output data RAM PERAM1 ROMMPLD(1990) WASMIIRAM(1992)Xilinx(1997) NECDRL(1998)Chameleon CS2112(2000) PE Logic cells Multiplexer 1 2 n Context Input data SRAM slots

33 ReCSiP ERATO( 10 PCIPC Biochemical Simulation) PC10

34 Biochemical Simulations () S1 S1 R1 S2 S2 R2 S3 S3 S3 S3

35 Kinetic Formula or, Rate-law function ex) v=(skm)/(s+vm) SS Km, Vm Enzyme P P

36 Example Mitotic Oscillator Model (Goldbeter, 1991) C, M, X 3 7 Cyclin Cyclin E1 E1 M* M* M E2 E2 M: cdc2 kinase X: Cyclin kinase * represents inactive X* X* X E4 E4

37 Simulation [X] [X] f[x] f[x] d[x] d[x] dt dt [X] [X] t t+ t

38 System Overview Optimal circuit, Always SBML SBML Description: XML-Based standard to markup biochemical pathways Lib. Lib. Solver Core Library: Verilog-HDL modules to calculate rate-raw functions I/F Software I/F Software Software Interface: Generate circuit and dataset from SBML description FPGA PCI Card: Configuration and dataset are loaded by I/F software. Here is result!

39 SBML <listofreactions> <reaction id="r01"> <listofreactants> <speciesreference species="x0" stoichiometry="1"/> </listofreactants> <listofproducts> <speciesreference species="s1" stoichiometry="1"/> </listofproducts> <kineticlaw formula= mass(x0,k1) > <listofparameters> <parameter id="k1" value="0.0033"/> </listofparameters> </kineticlaw> </reaction> </listofreactions>

40 ReCSiP Board 2002 XC2V bit/66MHz PCI -8 18Mb SRAM -64MB SDRAM

41 ReCSiP-2 Board 2003, 2004 XC2VP70 64bit/66MHz PCI -8 18Mb QDR-SRAM - SO-DIMM - (FDK)

42 Problem PCI Bandwidth Bottleneck FPGA PCI Host - - PCI PCI PCI Card - -

43 Requirements Stand-alone Processing Ability of FPGA hardcoding

44 Organization Using Multiple Solvers Solver Solver S1 S1 R1 S2 S2 R2 S3 S3 S3 S3 Core0 Idt0 Switch Idt1 Core1

45 Solver Core Pipelined Rate-Law Function Module S, VmV Adder Adder v=(skm)/(s+v )/(S+Vm) Multiplier S, KmK Divider v

46 Integrator Basic Mechanism Phase 1: [X] [X] Core Core d[x] d[x] Phase 2: [X] [X] FPADD d[x] d[x] 1~2k words FPGA BlockRAM

47 Integrator Control Method Counte rr Pathway [X] [X] Core Core d[x] d[x]

48 Integrator Pathway RAM: the Key Technology S1 S1 S2 S2 S3 S3 k1 k2 X k S END Pathway RAM X 0 S1 1 S2 2 S3 [X] RAM X 0 k1 1 k2 k RAM S 0 t 1 - t 2 2 t S RAM Solver Core Core

49 Requirements Stand-alone Processing Ability of FPGA FPGA hardcoding

50 Integrator Euler s Method k = f( x(t) ) x( t+ t ) = x(t) + k x(t+ t) k x(t)

51 Integrator Euler s Method 11 k k SS Phase 1 [X] [X] Core Core x + d[x] d[x] SS Phase 2 [X] [X] ++ x x d[x] d[x]

52 Integrator Heun s Method (or, Modified Euler) Euler k1 = f( x(t) ) k2 = f( x(t) + k1 ) x(t+ t) = x(t) + ( k1+k2 )/2 k1 k2 x(t+ t) x(t)

53 Integrator Heun s Method (or, Modified Euler) [X] d[x] 2 [X]1 [X]1 [X]2 [X]2 Core Core d[x]1 d[x]1 d[x]2 d[x]2 [X]1 [X]1 [X]2 [X]2 Step 1, Phase 1 Step 1, Phase 2 ++ d[x]1 d[x]1 d[x]2 d[x]2 [X]1 [X]1 [X]2 [X]2 Core Core d[x]1 d[x]1 d[x]2 d[x]2 [X]1 [X]1 [X]2 [X]2 Step 2, Phase 1 Step 2, Phase 2 ++ /2 /2 ++ d[x]1 d[x]1 d[x]2 d[x]2

54 Requirements Stand-alone Processing Ability of FPGA FPGA hardcoding

55 Switch Memory-to-Memory Communication Dual-port RAM k k SS Phase 1 [X] [X] Core Core x + d[x] d[x] SS Phase 2 [X] [X] ++ x x d[x] d[x]

56 Switch Organization Solver Core0 Idt0 Core3 Idt3 Idt1 Core1 Core2 Idt2

57 Switch Mapping and Scheduling S1 S1 S1 S2 S2 S2 S3 S3 S3 S3 S3 S3 R1 R1 R2 R2 Idt1 Idt1 Idt1 Core1 Core1 Core1 Idt0 Idt0 Idt0 Core0 Core0 Core0 Switch Switch Switch S3 S3 S3 S1 S1 S1 R1 R1 R1 R2 R2 R2 S2 S2 S2 S2 S2

58 Switch Solver-Transceiver-Crossbar Transceiver Code RAM Pathway RAM Code Code RAM RAM Solver Address WE Din Dout Transceiver Dest. Din Dout Crossbar

59 Requirements Stand-alone Processing Ability of FPGA FPGA hardcoding

60 Hardware Resources Minimal Mitotic Oscillator + Euler 63.7%

61 Hardware Resources Average Case XC2VP70 3~6 Solver Integrator Solver # solvers Core * Euler ~6 Heun (average) 4~5 RK ~4 * XC2VP70 has slices. Performance: Usually 90MHz+ with XC2VP70-5, 100MHz+ with XC2VP70-6.

62 Performance Replacing µps Pentium480 FPGA 1PC Integrator Pentium4 3.2GHz ReCSiP 90MHz Gain Euler Heun RK (Mreactions/sec.)

63 IEEE FPL2007FPT2007

64 FPT2007 ( Terak El-GhazawiGeorge Washington Univ.)High-Performance Reconfigurable ComputingTutorial

PLDとFPGA

PLDとFPGA PLDFPGA 2002/12 PLDFPGA PLD:Programmable Logic Device FPGA:Field Programmable Gate Array Field: Gate Array: LSI MPGA:Mask Programmable Gate Array» FPGA:»» 2 FPGA FPGALSI FPGA FPGA Altera, Xilinx FPGA DVD