Microsoft Word SOIまとめ.doc
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1 19 (SOI Pixel ) (4.9 revised) [ ] KEK :, JAXA Univ. of Hawaii : Gary Varner, Elena Martin, Stanford Linear Accelerator Center : Hiro Tajima [ ] (KEK) (JAXA) (1) SOI (Silicon-On-Insulator) Pixel/Strip/Frontend Electronics ( 1) β (2) SOI Pixel ( 1) 2 (3) KEK MPW(Multi Project Wafer) LBL, FNAL 17 ( 3 2) TCAD SOI KEK SOI Detector R&D Workshop Hawaii Univ., LBL, FNAL, BNL Workshop 4 ( 'kek'/'!kek#japan') Appendix - 1 -
2 1 SOI Pixel /27-30 (KEK) SNIC06 SLAC 4/3-6 (KEK) FEE2006 Perugia 5/15-19 JAXA) STD6 Carmel 9/11-15 (KEK) (KEK) (JAXA) Vertex 2006 Perugia 9/25-29 (KEK) LECC Valencia 9/25-29 IEEE NSS San Diego 10/29-11/4 (KEK) Hawaii 10/29-11/4, KEK) Vienna Conference on Vienna /19-24 KEK) Instrumentation 3/25-28 (KEK) ( 2 (1) "First Results of 0.15um CMOS SOI Pixel Detector", Y. Arai, M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S. Terada, T. Tsuboyama, Y. Unno, H. Ushiroda, H. Ikeda, K. Hara, H. Ishino, T. Kawasaki, E. Martin, G. Varner, H. Tajima, M. Ohno, K. Fukuda, H. Komatsubara, J. Ida, SNIC Symposium, Stanford, California, 3-6 April 2006, SLAC-PUB-12079, KEK preprint, , SLAC Electronic Conference Proceedings Archive (SLAC-R-842, econf: C ) PSN (2) "Development of a CMOS SOI Pixel Detector", Y. Arai, M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S. Terada T. Tsuboyama, Y. Unno, Y. Ushiroda, H. Ikeda, K. Hara, H. Ishino, T. Kawasaki, H. Miyake, E. Martin, G. Varner, H. Tajima M. Ohno, K. Fukuda, H. Komatsubara, J. Ida, Proceedings of 12th Workshop on Electronics for LHC and Future Experiments (LECC 2006), September 2006, Valencia SPAIN. (3) "R & D of a pixel sensor based on 0.15 m fully depleted SOI technology", Toru Tsuboyama, Yasuo Arai, Koichi Fukuda, Kazuhiko Hara, Hirokazu Hayashi, Masashi Hazumi, Jiro Ida, Hirokazu Ikeda, Yoichi Ikegami, Hirokazu Ishino, Takeo Kawasaki, Takashi Kohriki, Hirotaka Komatsubara, Elena Martin, Hideki Miyake, Ai Mochizuki, Morifumi Ohno, Yuuji Saegusa, Hiro Tajima, Osamu Tajima, Tomiaki Takahashi, Susumu Terada, Yoshinobu Unno, Yutaka Ushiroda and Gary Varner. Sep. 2006, Perugia, Italy, Vertex 2006, submitted to Nucl. Instr. and Meth. A. (4) "Monolithic Pixel Detector in a 0.15µm SOI Technology", Y. Arai, M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S. Terada, T. Tsuboyama, Y. Unno, H. Ushiroda, H. Ikeda, K. Hara, H. Ishino, T. Kawasaki, E. Martin, G. Varner, H. Tajima, M. Ohno, K. Fukuda, H. Komatsubara, J. Ida, H. Hayashi, IEEE Nuclear Sci. Symposium, San Diego, Oct Nov. 4, 2006, Conference Record. (5) "Evaluation of OKI SOI Technology", Y. Ikegami et al., presented at the 6th Hiroshima symposium of Development and Application of semiconductor tracking devices, Sep , 2006, Carmel, California, U.S.A., and submitted for publication in Nucl. Instr. Meth. (6) "R&D of a pixel sensor based on 0.15 mfully depleted SOI technology", Toru Tsuboyama, Yasuo Arai, Koichi Fukuda, Kazuhiko Hara, Hirokazu Hayashi, Masashi Hazumi, Jiro Ida, Hirokazu Ikeda, Yoichi Ikegami, Hirokazu Ishino, Takeo Kawasaki, Takashi Kohriki, Hirotaka Komatsubara, Elena Martin, Hideki Miyake, Ai Mochizuki, Morifumi Ohno, Yuuji Saegusa, Hiro Tajima, Osamu Tajima, Tomiaki Takahashi, Susumu Terada, Yoshinobu Unno, Yutaka Ushiroda and Gary Varner, submitted to Nucl. Instr. and Meth A
3 1 SOIPIX 3 1 MPW Top Cell Name Chip size Affiliation Designer(s) VARPIXEL 2.4 mm Osaka Univ. H. Miyake TOPPIXN 2.4 mm KEK Y. Arai OKI mm Tokyo Univ. H. Takahashi, K. Shimazoe, Fuiwara Achip 2.4 mm LBL P. Denes OKI_TOP 2.4 mm FNAL(BNL) G. Deptuch ATEG 2.4 mm JAXA/ISAS H. Ikeda BTEG 2.4 mm JAXA/ISAS H. Ikeda CTEG 2.4 mm JAXA/ISAS H. Ikeda isas_set mm JAXA/ISAS D. Kobayashi RADFET1 2.4 mm KEK T. Tsuboyama HawaiiNSUBSTRATE 5.0 mm Univ. of Hawaii E. Martin, G. Varner detectorpoly 5.0 mm KEK T. Tsuboyama TOP_PIXELSTRIP 5.0 mm KEK Y. Ikegami, Y. Arai TOP_8PREAMP 5.0 mm KEK Y. Ikegami TOPTEG2 5.0 mm KEK Y. Arai TOPINTPIX 5.0 mm KEK Y. Arai TOPCOUNT 10.2 mm KEK Y. Arai - 3 -
4 2 12 (10mm 4 SOI Detector R&D Workshop ( ) First SOI Detector R&D Workshop (Tuesday 06 March 2007)(KEK(Bldg. 3 Seminar Hall)) Session 1 10:00 Opening Remark (Takahiko Kondo (KEK, Head Physics Division II) ) 10:10 SOI Detector R&D : Past & Future (Yasuo ARAI (KEK) ) 10:40 Oki Fully Depleted SOI Technology for Ultra Low Power Applications (Jiro Ida (OKI Electric Industru Co. Ltd.) ) 11:20 SOI Strip Test & Design (Toru Tsuboyama (KEK) ) 11:50 Front-end circuit design in FD-SOI (Hirokazu Ikeda (JAXA/ISAS) ) Session 2 13:30 SOI Pixel Design : Univ. of Hawaii (video) (Elena Martin (Univ. of Hawaii) ) 13:55 SOI Pixel Design : LBL (video) (Peter Denes (LBL) ) 14:15 SOI Pixel Design : FNAL/BNL (video) (Grzegorz Deptuth (BNL(FNAL)) ) 14:35 Design of High Voltage MOS Transistor using TCAD (Hirokazu Hayashi (OKI Electric Industru Co. Ltd.) ) 14:55 SOI Detector Simulation by ENEXSS (Masashi Hazumi (KEK) ) Session 3 15:40 SOI Pixel Design : X-ray Counting Pixel (Yasuo Arai (KEK) ) 16:00 SOI Radiation Damage Test & Chip Design (Youichi Ikegami (KEK) ) 16:25 Discussion : Future Collaboration (Yasuo Arai (KEK) ) 16:45 Summary (Junji Haba (KEK) )
5 SOI st MPW TEG /X MPW MPW(Multi Project Wafer, 0.15um 2.3. ATLAS Si SOI Pixel (~100um) 2.4. TCAD Simulation 3 TCAD(ENEXSS) / GEANT - 5 -
6 SOI Detector R&D: Past & Future 1st SOI Detector R&D Workshop KEK, Mar. 6, 2007 Yasuo Arai (KEK) KEK Detector Technology Project : [SOIPIX Group, Y. Arai, Y. Ikegami, H. Ushiroda, Y. Unno, O. Tajima, T. Tsuboyama, S. Terada, M. Hazumi, T. Kohriki, H. Ikeda A, K. Hara B, H. Ishino C, T. Kawasaki D, H. Miyake B, K. Hanagaki H, Gary Varner E, Elena Martin E, Hiro Tajima F, Y. Hayashi G, M. Ohno G, K. Fukuda G, H. Komatsubara G, J. Ida G KEK, JAXA A, U. Tsukuba B, TIT C, Niigata U. D, U. Hawaii E, SLAC F,OKI Elec. Ind. Co. G, Osaka Univ. H yasuo.arai@kek.jp 1 OUTLINE 1. History 2. SOI Pixel Process 3. FY05 MPW Run 4. FY06 MPW Run 5. Summary yasuo.arai@kek.jp 2
7 Two Years ago... Unno san said (Detector April 2005) SOI Monolitic Detector! History '05.4: Detector R&D Express interests on SOI Pixel. 5: Create SOIPIX group, and propose SOI Pixel R&D to KEK Detector Technology Project (Generic R&D). 6: Negotiate with OKI Electric Industry Co. Ltd. 7: Start SOI detector R&D with OKI. 10: First TEG designs submitted for 0.15µm SOI CMOS process. '06.1: Characteristics of substrate p-n junctions were measured successfully. ENEXSS TCAD simulator was introduced. 3: Process of the 1st TEG chips was finished
8 History(2) '06.4-7: Response to Laser light was measured in strip TEG. First Picture was taken with 32x32 SOI Pixel. Good response to Sr 90!-ray was confirmed. 4-10: Presentation at conferences (SNIC06, STD6, Vertex, LECC, NSS, JSP...) 12: 2nd TEG Submissions by Multi Project Wafer (MPW) run with 17 designs. '07.3 : 2nd TEG process is almost finished. --> Test now! yasuo.arai@kek.jp 5 --> Ida san's Talk Feature of SOI! Full Dielectric Isolation : Latchup Free, Small Area! Low Junction Capacitance : High Speed, Low Power! No Well junction, Thin Film : Low Leakage, Low Vth Shift (~300 ºC)! Small Active Volume : High Soft Error Immunity yasuo.arai@kek.jp 6
9 SOI Wafer Fabrication!UNIBOND TM, SOITEC" microbubbles hydrophilic bonding ~500 o C CMOS (Low R) Sensor (High R) yasuo.arai@kek.jp 7 Features of SOI Monolithic Pixel detector! Bonded Wafer (High Resistive Substrate + Low Resistive Top Si).! Standard CMOS Electronics (NMOS, PMOS, MIM Cap etc. can be used).! Monolithic Detector, No Bump Bonds (Lower cost, Thin Device).! High density (Smaller Pixel Size is possible).! Small capacitance of the sense node (High gain V=Q/C)! Industrial standard technology (Cost benefit and Scalability) Explore possibility of SOI detector for future experiments (ILC, SLHC, Super-Belle etc.) and other applications (Medical, Material etc.) yasuo.arai@kek.jp 8
10 SOI Pixel Process Process SOI wafer Backside 0.15µm Fully-Depleted SOI CMOS process, 1 Poly, 5 Metal layers (OKI Electric Industry Co. Ltd.). Wafer Diameter: 150 mm", Top Si : Cz, ~18 #-cm, p-type, ~40 nm thick Buried Oxide: 200 nm thick Handle wafer: Cz!>1k #-cm (n-type), 650 µm thick (SOITEC) Thinned to 350 µm, and plated with Al (200 nm). p+/n+ Implant and Contact formation yasuo.arai@kek.jp 9 Metal contact & p+ implant Al yasuo.arai@kek.jp 10
11 p-n junction I-V characteristics n+ - back p+ - back " Good Diode Characteristic " Substrate is n type. ~700 #-cm (~6 x cm -3) yasuo.arai@kek.jp 11 FY05 MPW run 6"" MPW wafer 2.5 mm (chip) 20 µm (pixel) yasuo.arai@kek.jp 12
12 Pixel TEG CMOS Active Pixel Sensor Type 20 µm x 20 µm 32 x 32 pixels yasuo.arai@kek.jp 13 Pixel Layout Window for Light Illumination (5.4 x 5.4 um 2 ) p+ junction Storage Capacitance (100 ff) yasuo.arai@kek.jp 14
13 Pixel I-V characterisitic V break ~ 100 V Hot Spot observed with infrared camera I = 40 µa, T = 1 min Corner of the bias ring # Smooth the corner at next submission. (only 45 o allowed by design rule in previous run. next +30 o and 60 o ) yasuo.arai@kek.jp 15 Laser Image Plastic Mask 32x32 image view with 670nm Laser and plastic mask Vdet = 10 V Laser (670 nm) Exposure Time = 7 µs yasuo.arai@kek.jp 16
14 !-ray ( 90 Sr) Signals V sense = Q C " 0.6 fc 8 ff = 70mV Vdet = 10 V W depletion ~ 44 µm Q ~ 3500 e (0.6 fc) Expected signal amplitude was observed for!- ray yasuo.arai@kek.jp 17 Back Gate Effect Threshold Variation Back Gate Substrate Voltage act as Back Gate, and change transistor threshold. Signal disappears at 16V Consistent with SPICE simulation yasuo.arai@kek.jp 18
15 TCAD Simulations ENEXSS : 3D TCAD Simulator Back Gate effect can be reduced by placing p+ implant near transistors. D = (80, 5, 2 µm) NMOS BOX (200 nm) (5 µm wide p+, 1 x cm -3 ) Bulk: n- (~6 x cm -3 ) 350µm Backbias (0-100 V) Diode Electric Field yasuo.arai@kek.jp 19 Chip Thinning Moriya, Ibaraki (near Tsukuba) CMP : Chemical Mechanical Polishing --> ~30 µm thick yasuo.arai@kek.jp 20
16 Before Thinning 290 µm thick ATLAS Si Strip Thinning Test #$%&&%'()*+,%',-'.+ /0*12'%3%45627%82+,952.- After Thinning 100 µm thick FY06 SOI MPW Run :17 designs were submitted on Dec. 5, mm x 2.4 mm chips Oki (TEG1) Oki (TEG2) 5.0 mm x 5.0 mm --- ;6 chips 10.2 mm x 10.2mm --- ;1 chip =>< KEK (TEGs) Pixel (KEK) Preamp (KEK) Hawaii (KEK) Strip (KEK) Photon Counting <Pixel (KEK) JAXA Oki (TEG3) StripPix (KEK)?@A BCD Tr TEG (KEK) LBL FNAL 20.8 mm yasuo.arai@kek.jp 22
17 Top Cell Name Chip size Affiliation Designer(s) VARPIXEL 2.4 mm Osaka Univ. H. Miyake TOPPIXN 2.4 mm KEK Y. Arai OKI mm Tokyo Univ. H. Takahashi, K. Shimazoe, Fuiwara Achip 2.4 mm LBL P. Denes OKI_TOP 2.4 mm FNAL(BNL) G. Deptuch ATEG 2.4 mm JAXA/ISAS H. Ikeda BTEG 2.4 mm JAXA/ISAS H. Ikeda CTEG 2.4 mm JAXA/ISAS H. Ikeda isas_set mm JAXA/ISAS D. Kobayashi RADFET1 2.4 mm KEK T. Tsuboyama HawaiiNSUBSTRATE 5.0 mm U. of Hawaii E. Martin, G. Varner detectorpoly 5.0 mm KEK T. Tsuboyama TOP_PIXELSTRIP 5.0 mm KEK Y. Ikegami, Y. Arai TOP_8PREAMP 5.0 mm KEK Y. Ikegami TOPTEG2 5.0 mm KEK Y. Arai TOPINTPIX 5.0 mm KEK Y. Arai TOPCOUNT 10.2 mm KEK Y. Arai Todays Talks! Future Issues Wafer Thinning --> Less material. Super-B, ILC... 3D Circuit --> Higher density. Prepare Radiation Hard Cell Library --> for Super-B, SLHC, Satellite... More sophisticated structure (Avalanche...) in SOI substrate? Go to much fine process < 0.15 µm? Larger Detector (Stitching?) Cost saving
18 Summary Since the SOI Detector R&D started, it will be 2 years shortly. At First MPW run(fy05), possibility of SOI pixel is confirmed. At Second MPW run(fy06), 17 designs had been submitted including designs by foreign lab. We are planning Third MPW run in this Autumn. We welcome more people to join this interesting technology yasuo.arai@kek.jp 25
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