3. Arria GX IEEE 49. (JTAG) AGX523-. PCB PCB Bed-of-nails PCB 98 Joint Test Action Group (JTAG) IEEE Std. 49. (BST) PCB BST 3 3. IEEE Std. 49. Serial Data In Boundary-Scan Cell IC Pin Signal Serial Data Out Core Logic Core Logic Tested JTAG Device Connection JTAG Device 2 Altera Corporation 3
IEEE Std. 49. BST Arria GX IEEE Std. 49. BST IEEE Std. 49. BST IEEE Std. 49. IEEE Std. 49. BST JTAG I/O IEEE Std. 49. BST IEEE Std. 49. BST IEEE Std. 49. BST BSDL (Boundary Scan Description Language) BST Arria GX ICR IEEE Std. 49. IEEE Std.49. BST IEEE Std. 49. Arria GX Arria GX Volume 2 Arria GX JTAG Arria GX Stratix II Stratix II GX Stratix Cyclone II Cyclone JTAG 7 JTAG Arria GX Stratix II Stratix II GX Stratix Cyclone II Cyclone 8 SignalTap II IEEE Std. 49. BST IEEE Std. 49. BST Arria GX TDI TDO TMS TCK 4 TRST TCK TDI TMS TRST TDO I/O 4 V CCIO JTAG 3.3 V V CCPD JTAG I/O 3 2 Altera Corporation Arria GX Volume 2
Arria GX IEEE 49. (JTAG) JTAG 3 9 JTAG I/O 3 3. IEEE Std. 49. TDI TCK TDO TCK TMS TAP (Test Access Point) TCK TCK TMS TMS TCK TCK BST TRST Low Low JTAG GND IEEE Std. 49. BST TDI TDO Altera Corporation 3 3 Arria GX Volume 2
IEEE Std. 49. BST 3 2 IEEE Std. 49. 3 2. IEEE Std. 49. Instruction Register () TDI UPDATEIR CLOCKIR SHIFTIR TDO TMS TCLK TRST () TAP Controller UPDATEDR CLOCKDR SHIFTDR Instruction Decode Data Registers Bypass Register Boundary-Scan Register () a Device ID Register ICR Registers 3 2 : () IEEE Std. 49. TAP TAP 3 8 IEEE Std. 49. BST TMS TCK TAP TDI TDO TDI 3 4 Altera Corporation Arria GX Volume 2
Arria GX IEEE 49. (JTAG) IEEE Std. 49. TDI TDO Arria GX I/O 3 Arria GX Arria GX Volume 3 3 IEEE Std. 49. 3 3. Internal Logic Each peripheral element is either an I/O pin, dedicated input pin, or dedicated configuration pin. TAP Controller TDI TMS TCK TRST () TDO Altera Corporation 3 5 Arria GX Volume 2
IEEE Std. 49. Arria GX I/O Arria GX 3 BSC OUTJ OEJ PIN_IN PIN_OUT PIN_OE IEEE Std. 49. BST TAP MODE SDI SDO TDI TDO 3 4 Arria GX I/O 3 4. Arria GX IEEE Std. 49. BST I/O BSC Capture Registers SDO Update Registers INJ PIN_IN D Q D Q INPUT INPUT From or To Device I/O Cell Circuitry And/Or Logic Array OEJ D OE Q D OE Q V CC PIN_OE OUTJ D Q OUTPUT D Q OUTPUT PIN_OUT Output Buffer Pin SDI SHIFT CLOCK UPDATE HIGHZ MODE Global Signals 3 6 Altera Corporation Arria GX Volume 2
Arria GX IEEE 49. (JTAG) 3 2 Arria GX 3 2. Arria GX () Output Capture OE Capture Input Capture Output Update OE Update Input Update I/O OUTJ OEJ PIN_IN PIN_OUT PIN_OE INJ NA PIN_IN N.C. (2) N.C. (2) N.C. (2) PIN_IN (3) PIN_IN N.C. (2) N.C. (2) N.C. (2) PIN_IN (4) OEJ PIN_IN N.C. (2) N.C. (2) N.C. (2) PIN_IN (5) OUTJ OEJ PIN_IN N.C. (2) N.C. (2) N.C. (2) PIN_IN OUTJ (6) OUTJ N.C. (2) N.C. (2) N.C. (2) OUTJ 3 2 : () TDI TDO TMS TCK V CC GND VREF TEMP_DIODE BSC (2) N.C. (3) PLL_ENA nconfig MSEL MSEL MSEL2 MSEL3 nce VCCSEL PORSEL nio_pullup (4) CONF_DONE nstatus (5) DCLK (6) nceo Altera Corporation 3 7 Arria GX Volume 2
IEEE Std. 49. BST IEEE Std. 49. BST Arria GX IEEE Std. 49. BST SAMPLE/PRELOAD EXTEST BYPASS IDCODE IEEE Std. 49. USERCODE IEEE Std. 49. CLAMP TDI TDO HIGHZ I/O BST BST Arria GX Volume IEEE Std. 49. TAP TCK 6 TMS IEEE Std. 49. 3 5 TAP 3 8 Altera Corporation Arria GX Volume 2
Arria GX IEEE 49. (JTAG) 3 5. IEEE Std. 49. TAP TEST_LOGIC/ TMS = RESET TMS = SELECT_DR_SCAN TMS = SELECT_IR_SCAN TMS = RUN_TEST/ IDLE TMS = TMS = TMS = TMS = TMS = CAPTURE_DR TMS = CAPTURE_IR TMS = TMS = SHIFT_DR TMS = SHIFT_IR TMS = TMS = TMS = EXIT_DR TMS = TMS = EXIT_IR TMS = TMS = PAUSE_DR TMS = PAUSE_IR TMS = TMS = TMS = TMS = EXIT2_DR TMS = EXIT2_IR TMS = TMS = TMS = UPDATE_DR TMS = UPDATE_IR TMS = TMS = TAP TEST_LOGIC/RESET BST IDCODE TAP TEST_LOGIC/RESET TMS 5TCK High TRST Low TAP TEST_LOGIC/RESET TEST_LOGIC/RESET TAP TMS High TCK TRST Low Altera Corporation 3 9 Arria GX Volume 2
IEEE Std. 49. BST 3 6 IEEE Std. 49. 3 6. IEEE Std. 49. TMS TDI t JCP t JPSU_TDI t JCH t JCL t JPSU_TMS t JPH TCK t JPZX t JPCO t JPXZ TDO Signal to be Captured Signal to be Driven t JSZX t JSSU t JSH t JSCO t JSXZ IEEE Std. 49. TAP (SHIFT_IR) TDI 3 7 3 7 TCK TMS TDI TDOTAP RESET SHIFT_IR TAP TMS 3 Altera Corporation Arria GX Volume 2
Arria GX IEEE 49. (JTAG) 3 7. TCK TMS TDI TDO TAP_STATE SHIFT_IR RUN_TEST/IDLE SELECT_IR_SCAN TEST_LOGIC/RESET SELECT_DR_SCAN CAPTURE_IR EXIT_IR TDOSHIFT_IR SHIFT_DR TDO TCK TCK SHIFT_IR TDO TCK TDO SHIFT_IR TAP TMS Low SHIFT_IR SHIFT_IR TCK TDI EXIT_IR EXIT_IR TMS High EXIT_IR TDO TDO SHIFT_IR SHIFT_DR TAP 3 3 3 2 SAMPLE/PRELOAD 3 5 EXTEST 3 7 BYPASS Altera Corporation 3 Arria GX Volume 2
IEEE Std. 49. BST SAMPLE/PRELOAD SAMPLE/PRELOAD EXTEST 3 8 SAMPLE/PRELOAD 3 2 Altera Corporation Arria GX Volume 2
Arria GX IEEE 49. (JTAG) 3 8. IEEE Std. 49. BST SAMPLE/PRELOAD SDO OEJ OUTJ CLOCK TAP CLOCKDR OEJ OUTJ D Q D Q D Q D Q D Q D Q INJ Capture Registers Update Registers OEJ OUTJ CLOCK TDO TDI OEJ SDI SHIFT CLOCK UPDATE SDO D Q D Q D Q D Q MODE INJ UPDATE UPDATE UPDATE EXTEST OUTJ SDI SHIFT CLOCK D Q D Q Capture Registers UPDATE Update Registers MODE Altera Corporation 3 3 Arria GX Volume 2
IEEE Std. 49. BST TDO TDI EXTEST 3 5 EXTEST 3 9 SAMPLE/PRELOAD SAMPLE/PRELOAD TDI TAP CAPTURE_DR SHIFT_DR TMS Low SHIFT_DR TDO TDI TDO 3 9 TDI TDO TMS 2 TCK High TAP UPDATE_DR 3 9. SAMPLE/PRELOAD TCK TMS TDI TDO SHIFT_IR TAP_STATE EXIT_IR SELECT_DR Instruction Code UPDATE_IR CAPTURE_DR Data stored in boundary-scan register is shifted out of TDO. SHIFT_DR After boundary-scan EXIT_DR register data has been UPDATE_DR shifted out, data entered into TDI will shift out of TDO. 3 4 Altera Corporation Arria GX Volume 2
Arria GX IEEE 49. (JTAG) EXTEST EXTEST SAMPLE/PRELOAD EXTEST High Low 3 EXTEST Altera Corporation 3 5 Arria GX Volume 2
IEEE Std. 49. BST 3. IEEE Std. 49. BST EXTEST OEJ OUTJ CLOCK TAP CLOCKDR PIN_IN INJ I/O OEJ OUTJ SDO D Q D Q D Q D Q D Q D Q INJ OEJ SDI SHIFT CLOCK Capture Registers UPDATE Update Registers MODE SDO D Q D Q INJ OEJ OUTJ CLOCK TDO TDI OEJ OUTJ D Q D Q D Q D Q UPDATE PIN_IN INJ I/O SDI SHIFT CLOCK Capture Registers UPDATE Update Registers MODE 3 6 Altera Corporation Arria GX Volume 2
Arria GX IEEE 49. (JTAG) EXTEST SAMPLE/PRELOAD EXTEST EXTEST EXTEST SAMPLE/PRELOAD TDO 3 EXTEST SAMPLE/PRELOAD TDO TDI TDO 3. EXTEST TCK TMS TDI TDO SHIFT_IR TAP_STATE EXIT_IR SELECT_DR Instruction Code UPDATE_IR CAPTURE_DR Data stored in boundary-scan register is shifted out of TDO. SHIFT_DR After boundary-scan EXIT_DR register data has been UPDATE_DR shifted out, data entered into TDI will shift out of TDO. BYPASS BYPASS 3 2 TAP SHIFT_DR TCK TDI TDO Altera Corporation 3 7 Arria GX Volume 2
IEEE Std. 49. BST 3 2. BYPASS TCK TMS TDI TDO Bit Bit 2 Bit 3 Bit Bit 2 Bit 4 TAP_STATE SHIFT_IR EXIT_IR SELECT_DR_SCAN Instruction Code UPDATE_IR CAPTURE_DR SHIFT_DR Data shifted into TDI on the rising edge of TCK is shifted out of TDO on the falling edge of the same TCK pulse. EXIT_DR UPDATE_DR IDCODE IDCODE IEEE Std. 49. IDCODE ID 32 ID TDI TDO IDCODE IDCODE for Arria GX Arria GX Volume USERCODE USERCODE IEEE Std. 49. UES TDI TDO ID UES 32 USERCODE ID UES ID UES UES 3 8 Altera Corporation Arria GX Volume 2
Arria GX IEEE 49. (JTAG) CLAMP CLAMP TDI TDO CLAMP ( ) HIGHZ HIGHZ I/O JTAG TDI TDO HIGHZ JTAG I/O JTAG V CCIO TDO TDI TDI V CCPD 3.3 V Arria GX TDO 4 V CCIO 3 3 JTAG V CCIO TDI TDO V CCIO V CCIO JTAG TDO JTAG 3 3 JTAG Altera Corporation 3 9 Arria GX Volume 2
JTAG I/O 3 3. TDO/TDI TDI I/O 4 Arria GX TDO V CCIO V CCIO = 3.3 V V CCIO = 2.5 V V CCIO =.8 V V CCIO =.5 V Arria GX V CCPD (3.3 V) () (2) (3) Arria GX VCC = 3.3 V () (2) (3) VCC = 2.5 V () (4) (2) (3) VCC =.8 V () (4) (2) (5) VCC =.5 V () (4) (2) (5) (6) 3 3 : () TDO V OH (MIN) = 2.4 V (2) TDO V OH (MIN) = 2. V (3) 25 Ω (4) 3.3 V (5) 2.5 V (6).8 V 3 3. JTAG Must be 3.3 V Tolerant. TDI 3.3 V V CCIO 2.5 V V CCIO Tester TDO Level Shifter.5 V V CCIO.8 V V CCIO Shift TDO to level accepted by tester if necessary. Must be.8 V tolerant. Must be 2.5 V tolerant. 3 2 Altera Corporation Arria GX Volume 2
Arria GX IEEE 49. (JTAG) IEEE Std. 49. BST Arria GX JTAG IEEE Std. 49. BST Arria GX FPGA BST Arria GX FPGA BYPASS IDCODE SAMPLE JTAG CONFIG_IO CONFIG_IO JTAG I/O Arria GX FPGA JTAG-BST JTAG PULSE_CONFIG nconfig Low JTAG nconfig Low Arria GX DEV_CLRn DEV_OE JTAG BST BST JTAG Arria GX IEEE Std.49. Arria GX Volume 2 Arria GX BST I/O BSDL Altera Corporation 3 2 Arria GX Volume 2
IEEE Std. 49. BST Quartus II Quartus II. Settings Assignments 2. Assembler 3. Always Enable Input Buffers IEEE Std. 49. BST Arria GX IEEE Std. 49. BST IEEE Std. 49. BST BST 3 2 IEEE Std. 49. BST Arria GX IEEE Std. 49. 3 4 Arria GX IEEE Std. 49. 3 4. IEEE Std. 49. JTAG () TMS TCK TDI TDO TRST V CC GND V CC GND 3 4 : () Arria GX JTAG JTAG 3 22 Altera Corporation Arria GX Volume 2
Arria GX IEEE 49. (JTAG) IEEE Std. 49. IEEE Std. 49. SHIFT_IR TDO... TAP TAP SHIFT_IR TAP SHIFT_IR RESET TMS V CC GND JTAG EXTEST SAMPLE/PRELOAD EXTEST OEJ OUTJ ICR EXTEST ICR ICR CONFIG_IO nconfig Low BST BSC BSC BSDL (Boundary-Scan Description Language) Altera Corporation 3 23 Arria GX Volume 2
BSDL (Boundary Scan Description Language) BSDL (Boundary Scan Description Language) VHDL BSDL (Boundary-Scan Description Language) IEEE Std. 49. BST BSDL IEEE Std. 49. Arria GX BSDL www.altera.co.jp Arria GX IEEE Std. 49. BST IEEE Std. 49. EXTEST SAMPLE/PRELOAD BYPASS Bleeker, H., P. van den Eijnden, and F. de Jong. Boundary-Scan Test: A Practical Approach. Eindhoven, The Netherlands: Kluwer Academic Publishers, 993. Institute of Electrical and Electronics Engineers, Inc. IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std 49.-2). New York: Institute of Electrical and Electronics Engineers, Inc., 2. Maunder, C. M., and R. E. Tulloss. The Test Access Port and Boundary-Scan Architecture. Los Alamitos: IEEE Computer Society Press, 99. 3 24 Altera Corporation Arria GX Volume 2
Arria GX IEEE 49. (JTAG) 3 5 3 5. & v. N/A Altera Corporation 3 25 Arria GX Volume 2
3 26 Altera Corporation Arria GX Volume 2