コンポーネント・インタフェースTclリファレンス

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1 QII Tcl SOPC Builder Tcl _hw.tcl SOPC Builder _hw.tcl 1 SOPC Builder SOPC Builder 4 HDL _hw.tcl SOPC Builder C Tcl _sw.tcl 7 1 Tcl Tcl Tcl Tcl Tcl Basic component information HDL Altera Corporation 7 1

2 Quartus II Volume 4 Parameter Declarations SOPC Builder Verilog HDL VHDL Generics Interface Properties Avalon Memory-Mapped Avalon-MM waite-states Tcl SOPC Builder Main Program SOPC Builder _hw.tcl Tcl SOPC Builder Edit SOPC Builder Validaton Elaboration SOPC Builder Elaboration Generation Generation Quartus II HDL VHDL Verilog HDL RTL _hw.tcl 5 UART 7 2 Altera Corporation

3 Tcl _hw.tcl SOPC Builder 7-1. # The name and version of the component set_module_property NAME example_uart set_module_property VERSION 1.0 # The name of the component to display in the library set_module_property DISPLAY_NAME Example Component # The component s description. set_module_property DESCRIPTION An Example Component # The component library group that component belongs to set_module_property GROUP "Examples" _hw.tcl 7-2. # Declare the Baud Rate parameter as an integer with a # default value of add_parameter BAUD_RATE int 9600 # Display it as Baud Rate in the Parameter Editor. set_parameter_property BAUD_RATE DISPLAY_NAME Baud Rate (bps) # We only support three baud rates set_parameter_property BAUD_RATE ALLOWED_RANGES { } Altera Corporation 7 3

4 Quartus II Volume # Declare the clock sink interface, clock_sink, # type=clock, direction=sink # add_interface clock_sink clock sink # The clock interface has two signals, named clk and # reset_n, # of types clk and reset_n, both inputs of width 1 bit. add_interface_port clock_sink clk clk input 1 add_interface_port clock_sink reset_n reset_n input 1 # Declare the Avalon slave interface, # name= avalon_slave_0, type=avalon, directon=slave, # associated with the clock_sink clock interface. add_interface avalon_slave_0 avalon slave clock_sink # Set a number of properties about the Avalon Slave interface set_interface_property avalon_slave_0 writewaittime 0 set_interface_property avalon_slave_0 addressalignment DYNAMIC set_interface_property avalon_slave_0 readwaittime 1 set_interface_property avalon_slave_0 readlatency 0 # Declare all the signals that belong to my Avalon # Slave interface add_interface_port avalon_slave_0 readdata readdata output 32 add_interface_port avalon_slave_0 read read input 1 add_interface_port avalon_slave_0 write write input 1 add_interface_port avalon_slave_0 waitrequest waitrequest output 1 add_interface_port avalon_slave_0 address address input 7 add_interface_port avalon_slave_0 writedata writedata input Altera Corporation

5 Tcl Tcl HDL Synopsys Design Constraint.sdc HDL 7-4. # Add the HDL file to the component, to be used for # synthesis and simulation. add_file simple_uart.v {SYNTHESIS SIMULATION} # Timequest file with Quartus timing constraints. add_file simple_uart.sdc {SDC} # The top-level HDL file that describes the file, and # the name of the top-level module/entity. set_module_property TOP_LEVEL_HDL_FILE simple_uart.v set_module_property TOP_LEVEL_HDL_MODULE simple_uart _hw.tcl SOPC Builder Edit Validation Elaboration Generation SOPC Builder Altera Corporation 7 5

6 Quartus II Volume 4 Edit SOPC Builder Edit GUI 7 1 SOPC Builder GUI 7 1. TYPE DISPLAY_NAME ALLOWED_RANGES GROUP VISIBLE ENABLED GUI HDL add_parameter "1:3" GUI VISIBLE=0 GUI ENABLED=0 Validation SOPC Builder Validation ALLOWED_RANGES ALLOWED_RANGES start:end 7 6 Altera Corporation

7 Tcl 7 2 ALLOWED_RANGES 7 2. ALLOWED_RANGES ALLOWED_RANGES {a, b, c} {1, 2, 4, 8, 16} 1:3 1, 2, 3, 7:10 "a" "b" "c" Elaboration Elaboration SOPC Builder HDL SOPC Builder quartus_map quartus_ map AFFECTS_PORT_WIDTHS false quartus_map Generation Generation SOPC Builder TOP_LEVEL_MODULE SOPC Builder Verilog HDL VHDL SOPC Builder HDL TOP_LEVEL_MODULE SOPC Builder SOPC Builder Altera Corporation 7 7

8 Quartus II Volume 4 4 Edit Edit EDITOR_CALLBACK Edit SOPC Builder GUI Edit Tcl Tk GUI Edit GUI Edit GUI stdout GUI set_parameter_value SOPC Builder 7 8 Altera Corporation

9 7-5. set_module_property EDITOR_CALLBACK my_editor # Define Module parameters add_parameter PARAMETER_ONE integer "32" "A parameter" add_parameter CSR_ENABLED boolean "true" "Enable CSR interface" # My editor method proc my_editor { # get parameter values set p1 [ get_parameter_value "PARAMETER_ONE" ] set csr [ get_parameter_value "CSR_ENABLED" ] # Display UI, populated with current parameter # values. # The stdout returned by the UI program includes the # new paramter values. set result = [exec my_component_ui.exe p1=$p1 csr=$csr] # use the fictional parse_for_new_value procedure # to # parse the returned text for the new parameter # values. set p1 [parse_for_new_value $result p1 ] set csr [parse_for_new_value $result csr ] # Return the new parameter values to SOPC Builder set_parameter_value "PARAMETER_ONE" $p1 set_parameter_value "CSR_ENABLED" $csr } Validation Validation VALIDATION_CALLBACK Validation Validation Validation Validation Validation Altera Corporation 7 9

10 Quartus II Volume 4 Validation.sopc derived TRUE BAUDRATE_PRESCALE Validation BAUDRATE 1/ # Declare the validation callback. set_module_property VALIDATION_CALLBACK my_validation_callback # Add the BAUDRATE_PRESCALE parameter add_parameter BAUDRATE_PRESCALE int 600 set_parameter_property BAUDRATE_PRESCALE DERIVED true # The validation callback proc my_validation_callback { # Get the current value of parameters we care about set baudrate [get_parameter_value BAUD_RATE] set parity [get_parameter_value PARITY] # Display an error for invalid combinations. if {($baud_rate==38400) && ($parity== odd )} { send_message error Odd parity at bps is not supported. } # Set the value of our derived parameter set baudrate_prescale [expr $baud_rate / 16] set_parameter_value BAUDRATE_PRESCALE $baudrate_counter Elaboration Elaboration Elaboration ELABORATION_CALLBACK Elaboration _hw.tcl 7 10 Altera Corporation

11 Elaboration Avalon-MM USE_STATUS_INTERFACE Elaboration TRUE HDL Elaboration 7-7. # Declare the callback. set_module_property ELABORATION_CALLBACK my_elaboration_callback # Add the USE_STATUS_INTERFACE parameter add_parameter USE_STATUS_INTERFACE boolean # The elaboration callback proc my_elaboration_callback { # Get the current value of parameters we care about set use_status [get_parameter_value USE_STATUS_INTERFACE] # Optionally add an interface and HDL file. if { $use_status==1 } { # Declare the status slave interface add_interface status_slave avalon slave clock_sink # Set interface properties set_interface_property status_slave writewaittime 0 set_interface_property status_slave readwaittime 1 # Declare signals add_interface_port status_slave st_readdata readdata output 32 add_interface_port status_slave st_read read input 1 add_interface_port status_slave st_write write input 1 add_interface_port status_slave st_waitrequest waitrequest output 1 add_interface_port status_slave st_address address input 7 add_interface_port status_slave st_writedata writedata input 32 #Include the file that defines the status interface add_file my_status_interface.v {SYNTHESIS SIMULATION} } Altera Corporation 7 11

12 Quartus II Volume 4 } Generation Generation SOPC Builder HDL Generation Generation HDL GENERATION_CALLBACK Generation Generation Generation Generation Tcl HDL add_files SOPC Builder Generation 7 3 Generation 7 3. Generation HDL_LANGUAGE OUTPUT_DIRECTORY OUTPUT_NAME HDL Verilog VHDL HDL HDL comp_0 OUTPUT_NAME Generation comp_0 Generation comp_ Altera Corporation

13 Tcl Generation 7-8. set_module_property generationcallback my_generate # My generation method proc my_generate {} { send_message "info" "Starting Generation" # get generation settings set language [ get_generation_setting "HDL_LANGUAGE" ] set outdir [get_generation_setting "OUTPUT_DIRECTORY" ] set outputname [get_generation_setting "OUTPUT_NAME" ] # get parameter values set p1 [ get_parameter_value "PARAMETER_ONE" ] set csr [ get_parameter_value "CSR_ENABLED" ] # Do HDL generation with perl exec perl my_generate.pl lang=$language dir=$outdir name=$outputname p1=$p1 csr=$csr } add_file ${outputname}.v SYNTHESIS add_file ${outputname}_sim.v SIMULATION Tcl Tcl Generation Edit Validation Elaboration Generation Altera Corporation 7 13

14 Quartus II Volume 4 get_module_properties : get_module_propertyset_module_property : String[] : list_of_module_properties : get_module_properties / NAME DISPLAY_NAME VERSION AUTHOR DESCRIPTION GROUP ICON_PATH DATASHEET_URL my_sopc_component : My SOPC Component : 8.0 : Example SOPC Builder Module : Example Components 7 14 Altera Corporation

15 7 4. get_module_properties / EDITABLE MODULE_TCL_FILE MODULE_DIRECTORY TOP_LEVEL_HDL_FILE Validation Generation TOP_LEVEL_HDL_MODULE Validation Generation INSTANTIATE_IN_SYSTEM_MODULE VALIDATION_CALLBACK EDITOR_CALLBACK _hw.tcl _hw.tcl add_file HDL HDL false Validation Edit Altera Corporation 7 15

16 Quartus II Volume get_module_properties / ELABORATION_CALLBACK GENERATION_CALLBACK SIMULATION_MODEL_IN_VERILOG SIMULATION_MODEL_IN_VHDL Elaboration Generation True SOPC Builder Verilog HDL True SOPC Builder VHDL get_module_property : 1 : : get_module_property [propertyname} : Validation Edit Elaboration Generation : set my_name [get_module_property NAME] 7 16 Altera Corporation

17 set_module_property : : <void> : set_module_property [propertyname] [propertyname] : Validation 7 4 Generation 7 4 : set_module_property VERSION 8.0 add_file :.sdc Elaboration Generation Generation SIMULATION HDL SYNTHESIS HDL SDC TimeQuest QIP Quartus II IP : <void> : add_file filename [fileproperties] : Elaboration Generation Altera Corporation 7 17

18 Quartus II Volume 4 : add_file my_component.v {SIMULATION SYNTHESIS} get_files : : String[] : get_files [] : Validation Edit Elaboration Generation get_file_property : 1 /components/my_file.v my_file.v add_files : : get_file_property [filename] [propertyname] : Validation Edit Elaboration Generation : get_file_property my_file.v SYNTHESIS 7 18 Altera Corporation

19 set_file_property : 1 /components/my_file.v my_file.v add_files : <void> : set_file_property [filename] [propertyname] [propertyvalue] : Elaboration Generation : set_file_property my_file.v SYNTHESIS true send_message : Error: ToDoError: ToDo Info: Warning: Progress:Generation Debug: : <void> : send_message [messagelevel] [messagetext] : Validation Generation : send_message Error param1 must be greater than param2. Altera Corporation 7 19

20 Quartus II Volume 4 add_parameter : Verilog HDL Parameter VHDL Generics Integer Boolean Std_logic VHDL Std_logic_vector VHDL String : <void> : add_parameter [parametername] [parametertype] [defaultvalue description] : : add_parameter seed integer 17 The seed to use for data generation. get_parameters : add_parameter : String [] : get_parameters : Validation Edit Elaboration Generation 7 20 Altera Corporation

21 get_parameter_properties : parameter_properties get_parameter_property set_ parameter_property get_parameter_properties DISPLAY_NAME String ALLOWED_RANGES String GROUP String AFFECTS_PORT_ WIDTHS Boolean VISIBLE Boolean Validation ENABLED Boolean Validation 17 [11:15] quartus_map quartus_map true GUI false GUI : String [] : get_parameter_properties Altera Corporation 7 21

22 Quartus II Volume 4 : Validation Edit Elaboration Generation get_parameter_property : 1 : 7 5 : get_parameter_property [parametername] [propertyname] : Validation : get_parameter_property parameter1 GROUP set_parameter_property : 1 : <void> : set_parameter_property [parametername][propertyname] [value] : Validation : set_parameter_property parameter1 ALLOWED_RANGES {1, 2, 4, 8} 7 22 Altera Corporation

23 get_parameter_value : add_parameter : : get_parameter_value [parametername] : Validation Edit Elaboration Generation : get_parameter_value parameter1 set_parameter_value : Validation : <void> : set_parameter_value [parametername] [value] : Validation : set_parameter_value parameter1 4 Altera Corporation 7 23

24 Quartus II Volume 4 add_interface : 7 6 Type Direction 7 6. add_interrface Type Direction Type avalon avalon_tristate avalon_streaming interrupt conduit clock nios_custom_instruction Direction : <void> : add_interface interfacename interfacetype direction [associatedclock] : Elaboration : add_interface s0 avalon slave clock0 get_interfaces : add_interface : String[] : get_interfaces : Elaboration 7 24 Altera Corporation

25 get_interface_properties : Avalon Interface Specifications : String [] : get_interface_properties [interfacename] : Elaboration : get_interface_properties s0 get_interface_property : 1 : : get_interface_property [interfacename] [propertyname] : Elaboration : get_interface_property s0 readwaittime set_interface_property : 1 : <void> : set_interface_property interfacename apropertyname value Altera Corporation 7 25

26 Quartus II Volume 4 : Elaboration : set_interface_property s0 readwaittime 2 add_interface_port : Avalon Interface Specifications portdirection Input Output Bidir VHDL Buffer : <void> : add_interface_port [interfacename] [portname] [portrole direction] [Width] : Elaboration : add_interface_port s0 s0_rdata readdata output 32 get_interface_ports : : String[] : get_interface_ports [interfacename] : Elaboration 7 26 Altera Corporation

27 get_port_properties : DIRECTION Direction INPUT OUTPUT BIDIR BUFFER WIDTH Integer TERMINATION Boolean True SOPC Builder output & bidir inputs TERMINATION_ VALUE Long : String [] : get_port_properties portname : Elaboration : get_port_properties s0 get_port_property : : : get_port_property portname propertyname : Elaboration : get_port_property s0_rdata WIDTH Altera Corporation 7 27

28 Quartus II Volume 4 set_port_property : 1 : <void> : set_port_property portname propertyname value : Elaboration : set_port_property s0_rdata WIDTH 32 Generation get_generation_properties : get_generation_property get_generation_properties HDL_LANGUAGE Enum HDL vhdl verilog OUTPUT_DIRECTORY File OUTPUT_NAME String OUTPUT_NAME module_0 HDL_LANGUAGE VERILOG module_o.v module_0 : String [] : get_generation_properties 7 28 Altera Corporation

29 Generation : Generation get_generation_property : 1 : : get_generation_property propertyname : Generation get_project_property : get_project_property / QUARTUS_ROOTDIR String $QUARTUS_ROOTDIR QUARTUS_PROJECT_DIRECTORY String QUARTUS_PROJECT_NAME String Quartus II Altera Corporation 7 29

30 Quartus II Volume get_project_property / DEVICE_FAMILY_NAME Enum STRATIX STRATIXII STRATIXIIGX STRATIXIIGXLITE STRATIXGX STRATIXIII STRATIXIV CYCLONE CYCLONEII CYCLONEIII HARDCOPY HARDCOPYII HARDCOPYIII MAXII APEX20KE APEX20KC APEXII ACEX1K DEVICE_FAMILY_FEATURES Enum [ ] M512_MEMORY M4K_MEMORY M9K_MEMORY M144K_MEMORY MRAM_MEMORY MLAB_MEMORY ESB EPCS DSP EMUL HARDCOPY LVDS_IO ADDRESS_STALL TRANSCEIVER_3G_BLOCK TRANSCEIVER_6G_BLOCK DSP_SHIFTER_BLOCK : : get_project_property propertyname : Generation 7 30 Altera Corporation

31 Avalon Interface Specifications Nios II Nios II Software Build Tools Reference v8.0.0 _hw.tcl Tcl Tcl v v7.1.0 Altera Corporation 7 31

32 Quartus II Volume Altera Corporation

Avalon Memory-Mappedブリッジ

Avalon Memory-Mappedブリッジ 11. Avalon emory-apped QII54020-8.0.0 Avalon emory-apped Avalon- OPC Builder Avalon- OPC Builder Avalon- OPC Builder Avalon-11 9 Avalon- Avalon- 11 12 Avalon- 11 19 OPC Builder Avalon emory-apped Design