J. Jpn. Inst. Electron. Packaging 19(1): (2016)
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1 特特集 / エレクトロニクス実装技術の現状と展望 半導体システムインテグレーション技術における とその将来展望 FO-WLP in Semiconductor System Integration Technology and Its Future Prospects システムインテグレーション実装技術委員会 集 はじめに 1),2) MEMS (Micro Electro-Mechanical System) Fig. 1 3) Vol. 19 No. 1 (2016) 1990 Peripheral BGA (Ball Grid Array) CSP (Chip Scale/Size Package) Area 2000 SiP (System in Package) BEOL (Back End of Line) WLP (Wafer-Level Package) 4) WLP SiP 5),6) SoC (System on Chip) SiP SoC SiP WLP Multichip FOP (Fan-Out Package)- WLP RDL (Redistribution Layer) SoC SiP 7),8) FO-WLP
2 特集41 技術における Fig. 2 WLP 9) WLP BEOL WLP WLP Fig. 3 FI (Fan-In) WLP FI-WLP Peripheral I/O RDL I/O Area I/O I/O Fig. 4 FO (Fan-Out) WLP FO-WLP I/O FI-WLP I/O RDL FO-WLP I/O FI-WLP I/O (Tg) RDL Fig. 5 FO-WLP 10) FO-WLP I/O I/O RDL Multichip FO-WLP FC-BGA I/O I/O 3.0 mm 3.0 mm 2.5 mm 2.5 mm I/O 3.0 mm 3.0 mm Conventional package Wafer-level package Front-end process Silicon wafer process Front-end process Silicon wafer process Final BEOL process WLP** Die sort test wafer-level process Die sort test Function test Post process Wafer dicing Post process Wafer dicing Visual inspection Assembly Inspection Function test Visual inspection **WLP process + RDL (Redistribution layer) formation + Insulating layer formation + RDL pad opening + BLM (Ball Limiting metal) formation + Solder ball/reflow Packaging trends Virtual packaging design Flexible I/O pitch * LSI chip shrinkage Fan-In WLP WLP (Chip) size = 3.0mm x 3.0mm WLP size = 3.0mm x 3.0mm Chip size = 2.5mm 2.5mm Miniaturization and low-cost * Fine-pitch RDL System in Package SiP size = 12.0mm 12.0mm = 7.0mm 7.0mm Fine-pitch and large I/O number of LSI chip * Fine-pitch RDL Flip-Chip BGA Line/Space = 25μm/ 25μm Line/Space = 5μm/ 5μm Vol. 19 No. 1 (2016)
3 特 FO-WLP I/O 集 Multichip FO-WLP SiP 12.0 mm 12.0 mm FO-WLP 7.0 mm 7.0 mm FO-WLP SiP I/O FC-BGA Line/Space = 25 μm/25 μm FO-WLP RDL Line/Space = 5 μm/5 μm I/O 技術における擬似 技術 FO-WLP 11),12) ewlb (Embedded Wafer Level Ball Grid Array) 11) FO-WLP InFO 12) SoC 13) SiP Fig. 6 SoC SoC Memory, Power LSI MEMS CMOS-LSI KGD (Known Good Die) RDL 14),15) Fig. 7 SoC (KGD) 42 Vol. 19 No. 1 (2016) RDL I/O (Input/Output) SoC KGD Fig. 8 AFE (Analog Front End) SoC AFE EGG (Electrocardiogram) AFE Pulse AFE mm 7.3 mm 1 mm AFE SoC 16) Fig. 9 AFE SoC AFE SoC 6.3 mm Bluetooth TM AFE pseudo-soc 7.3 mm Acceleration sensor Solder Ball Micrograph of AFE pseudo-soc for Wearable Vital Signs Sensor
4 特集43 Polyimide Al pad LSI chip Circumference of embedded devices Contact pad Passive chip component Epoxy resin Epoxy resin Enlarged micrograph Contact pad Passive chip component LSI chip Al pad Acceleration senor MCU Chip on Board ECG AFE Chip on Board Pulse AFE Bluetooth TM Power unit ECG AFE = 12.0mm 6.0mm Pulse AFE = 10.0mm 5.0mm AFE footprint = 122mm 2 <100 > 15.0 mm Power unit Bluetooth TM AFE Pseudo-SoC Acceleration sensor 15.0 mm Pseudo-SoC (ECG, Pulse) = 6.3 mm 7.3 mm AFE footprint = 45.99mm 2 <38 > RDL RDL 17) Fig. 10 AFE COB (Chip on Board) SoC AFE ECG AFE 12.0 mm 6.0 mm Pulse AFE 10.0 mm 5.0 mm SoC AFE 6.3 mm 7.3 mm SoC 2 AFE 38% 17) の将来展望 SiP 2.5D/3D 18) Multichip FO-WLP 2.5D/3D 19) Fig. 11 FO-WLP SoC 3D 20) 3D 3D 3D Fig. 11 3D More Moore CPU Logic Memory CMOS-LSI More than Moore 21) Analog/RF Passives Sensor/Actuator HV/Power Biochips FO-WLP 20) FO-WLP More than Moore 3D 3D More Moore CMOS-LSI TSV (Through Silicon Via) More than Moore FO-WLP TMV (Through Mold Via) TMV TSV FO-WLP SoC 2.5D/3D Fig D/3D 20) DIP (Dual Inline Package) QFP (Quad Flat Package) SMT (Surface Mount Technology) 2 Vol. 19 No. 1 (2016)
5 特 1990 集BGA (Ball Grid Array)/CSP (Chip Scale/Size Package) I/O MCP (MultiChip Package)/ MCM (MultiChip Module) 2D 3D 2.5D 2.5D 3D 3D 2D FO-WLP 2.5D TSV (Through Silicon Via) RDL 2.1D 2.1 3D 2D 2.1D 2.5D/3D MoM (Module on Module) Multichip Chip on/in Film 22),23) 2.5D/3D-SiP Chip on/in Film 3D Film-SiP 3D-IC FO-WLP RDL 3D Film-SiP まとめ FO-WLP SiP ASSP (Application Specific System Package) FO-WLP ASSP 44 Vol. 19 No. 1 (2016) FO-WLP More than Moore IoT (Internet of Things) CPS (Cyber Physical System) FO-WLP CPS IoT CPS 謝辞 SoC (NEDO) MEMS 文献 1) Vol., No. 1, pp. 1 62, ) R. Tummala, E. Rymaszerski, and A. Klopfenstein Editors: Microelectronics packaging an overview, Microelectronics Packaging Handbook, chapter 1, pp , Chapman & Hall, London, U. K., ) C Vol., No. 11, pp , ) ) P. Garrou and R. Tummala: Fundamental of Wafer-level Packaging, Fundamentals of Microsystems Packaging, chapter 10, pp , McGraw Hill, NY, ) P. Garrou: Wafer Level Chip Scale Packaging (WL-CSP): An Overview, IEEE Transaction on Advanced Packaging Vol., No. 2, pp , May, ) MEMS
6 特集45 Vol., No. 1, pp , ) Jisso 2015 pp , ) Electronic Journal 1872 Technical Seminar ) Fan out-wlp ) M. Brunnbauer, E. Fürgut, G. Beer, and T. Meyer: "Embedded Wafer Level Ball Grid Array (ewlb), Electronics Packaging Technology Conference 2006, pp. 1 5, Singapore, December ) D. Yu: A New Integration Technology Platform: Integrated Fan- Out Wafer-Level-Packaging for Mobile Applications, Symposium on VLSI Technology 2015, pp , Kyoto, Japan, June ) H. Yamada, Y. Onozuka, A. Iida, K. Itaya, and H. Funaki: Wafer- Level Heterogeneous Technology Integration for Flexible Pseudo- SoC, Digest of Technical Papers of IEEE ISSCC 2010, pp , San Francisco, February ) H. Yamada, Y. Onozuka, A. Iida, K. Itaya, and H. Funaki: Wafer- Level Heterogeneous Technology Integration for Flexible Pseudo- SoC, Digest of Technical Papers of IEEE ISSCC 2010, pp , San Francisco, February ) H. Yamada, Y. Onozuka, A. Iida, K. Itaya, and H. Funaki: A Wafer-level System Integration Technology incorporates Heterogeneous Devices, Proceedings of IMAPS 2012, pp , San Diego, September ) H. Yamada, Y. Sato, N. Ooshima, H. Hirai, T. Suzuki, and S. Minami: Heterogeneous System Integration Pseudo-SoC Technology for Smart-health-care Intelligent Life Monitor Engine & Eco-system, IEEE ECTC 2014, Florida, May ) H. Yamada, Y. Sato, N. Ooshima, H. Hirai, T. Suzuki, and S. Minami: Heterogeneous System Integration Pseudo-SoC Technology for Smart-health-care Intelligent Life Monitor Engine & Eco-system, IEEE ECTC 2014, Florida, May ) H. Yamada: A wafer-level system integration (Pseudo-SoC) technology and its wearable intelligent smart sensor module application, Semicon Japan, Tokyo, December ) ) R. Aschenbrenner: Molding technologies a new way for system integration, Plenary Speech of ICSJ2012, Kyoto, November, ) H. Funaki, H. Yamada, Y. Onozuka, and K. Itaya: Hyper system integration technology for heterogeneous device integration, NEDO Highly Integrated, Complex MEMS Production Technology Project (Fine MEMS project) The 20th Micromachine MEMS Exhibition, Tokyo, Japan, July ) ITRS (International Technology Roadmap for Semiconductors), 2007 Edition 22) T. Löher, M. Seckel, R. Vieroth, C. Dils, C. Kallmayer, A. Ostmann, R. Aschenbrenner, and H. Reichl: Stretchable Electronic Systems: Realization and Applications, IEEE Electronics Packaging Technology Conference 2009, pp , Singapore, December ) T. Löher, D. Schütze, A. Ostmann, and R. Aschenbrenner: Module Miniaturization by ultra thin Package Stacking, IEEE CPMT Symposium Japan 2010, pp. 1 4, Tokyo, August 2010 著者紹介山田浩 D IMAPS IEEE IEEE CPMT Society Japan Chapter Vice Chair IEEE ICSJ General Chair JEITA IEEE Transaction on Advanced Packaging Best Paper Award (2004) IMAPS Best Paper Award (1997, 1999, 2000, 2009) SHM Outstanding Paper Award (1996) MES (1998) (2001) (2014) IEEE CPMT Symposium Japan Best Paper Award (2010) ICEP Outstanding Technical Paper Award (2012) (2005) (2008) (2013) IEEE Vol. 19 No. 1 (2016)
J. Jpn. Inst. Electron. Packaging 17(4): (2014)
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