1 1 2 2 2-1 2 2-2 4 2-3 11 2-4 12 2-5 14 3 16 3-1 16 3-2 18 3-3 22 4 35 4-1 VHDL 35 4-2 VHDL 37 4-3 VHDL 37 4-3-1 37 4-3-2 42 i

1030195 15 2 10

1 1 2 2 2-1 2 2-2 4 2-3 11 2-4 12 2-5 14 3 16 3-1 16 3-2 18 3-3 22 4 35 4-1 VHDL 35 4-2 VHDL 37 4-3 VHDL 37 4-3-1 37 4-3-2 42 i

4-3-3 47 5 52 53 54 55 ii

1 VHDL IC VHDL 5 2 3 IC 4 5 1

2 2-1 sequential circuit 2.1 [1] 2.1 2.1 t t t 2

state transition diagram state transition table 2.2 2.2 a s1 s3 3 2.2 b a 2.2 3

2-2 flip-flop FF 1 2.3 a 2 NOT N1 N2 N1 Q1 H N2 Q1 H Q2 L N1 L Q1 H Q1 Q1 H Q2 L Q1 L Q1 L Q2 H 2.3 a 2 2 2.3 b R S Q [5] 4

2.3 2 SR SR set reset flip-flop SR-FF S R 2.4 S 1 Q 1 R 0 Q 1 Q 1 FF Q 0 S R 1 S R 0 Q 1 Q 2.4 FF SR SR-FF 2.5 a Q 2.5 b 2.5 c 5

Q Q FF 2.5 d 2.5 SR 6

D D delayed flip-flop D-FF D CL CL D CL CL 1 2.6 a D-FF b c d CL FF 2.6 c SR-FF R Q D 7

2.6 D SR JK T SR S/R 0 Q S/R 1 0 / 1 S/R Q 1 / 0 2.7 SR-FF [2] 8

Q Q t+1 Q Q t Q Q S S R 0 2.7 SR 2.8 [2] 2.8 9

JK SR J/K J/K 0 SR J/K 1 Q SR D 2.9 JK-FF [2] Q Q J 2.9 JK T JK J K T T 0 Q T 1 Q toggle 2.10 T [2] 10

Q Q T T Q 2.10 T 2-3 2.11 latch register read write 2.11 D 11

1 1 D-FF 2.12 D-FF 4 [1] 2.12 2-4 Counter count 1 count up 1 count down 2 10 12 12

ripple carry 2.13 2.13 [2] [2] 13

2-5 decode 2 decoder 2.14 2 1 0 [2] 2.14 2 4 encode encoder 1 1 2.15 2 [2] 1 2.15 D1 D 2 1 D 0 D 3 0 Q 11 D3 14

priority D0 D3 D 1 D 2 1 Q 10 D2 2.15 4 2 15

3 3-1 1 6 2 3 2.5 1 6 1/6 3 3 1 6 ON 1 6 [6] 16

1 6 1 7 LED LED 6 LED 1 6 LED 3.1 LED 3.1 7 LED LED 3.2 LED LED LED LED [6] 3.2 LED 17

3-2 1 6 7 LED 1 6 LED 7 LED LED 1 6 LED 3.3 3.3 LED 7 LED a g 7 LED LED 3.4 3.4 b LED 2 4 5 6 [6] 18

3.4 LED 2 4 5 6 1 H 4 OR b f 1 OR a g 4 OR d 3 OR OR NAND OR NAND 3.5 OR NAND 19

3.5 OR NAND OR NAND OR NAND 3.6 3.7 4 NAND 74HC20 3 NAND 74HC10 NAND 1 330 LED LED 6 LED OFF NAND 0 3V 47k 1 NAND [6] 20

3.6 OR NAND [6] 21

3.7 [6] 3-3 3.8 3 3.9 H 22

3.8 3.9 1 6 6 1 6 6 000 2 101 2 6 1 6 6 LED 3.9 23

[6] CR CR CR CR 3.10 CR 4 74HC14 2 1M,100k 1 0.01 F 45Hz 3.10 CR 6 74 6 7492 TTL D 74HC74 6 6 24

D n=6 6 3.11 [6] 3.11 6 [6] 25

LED 6 10 0 000 2 5 101 2 6 LED 2 2 6 000 101 LED 7 2 LED LED 1 6 7 LED 3.11 7 LED a g X Y Z LED X 0 Y 0 Z 0 1 X 1 Y 0 Z 0 2 2 2 [6] 3.12 26

3.13 X Y Z 3 a b c d e f g 7 X Y Z 0 0 0 1 0 1 6 2 3bit 7bit 3-13 a b c d e f g 3.12 3.12 LED 1 LED 0 LED LED LED 1 LED 3.12 [6] 3.12 LED 3.14 3.15 [6] 27

X Y Z 3 0 0 0 1 1 1 8 6 1 1 0 1 1 1 1 3.14 [6] 28

3.15 3.15 Z OR a g 3.16 3.12 a g b f c e a g 7 4 3.16 b AND OR IC NAND NOR NAND 74HC00 1 3.16 c D [6] 29

3.16 LED LED IC 74HC04 IC H ON L 5V LED IC 470 LED 6mA [6] ON OFF CR 3.17 ON 4.7 F 0 5V 100k L H NAND OFF 4.7 F 100k 5V 30

ON OFF LED ON LED OFF L NAND [6] 3.17 CR 3.18 3.19 3.20 ON OFF 31

3.18 32

3.19 CR 3.20 3.20 6 33

ON,OFF LED LED 34

4 4-1 VHDL HDL HDL ASIC HDL ASIC FPGA PLD HDL VHDL VHSIC HDL Verilog-HDL UDL I Unified Design Language for Integrated Circuit SFL Structured Function description Language 4.1 VHDL [7] 4.1 HDL 35

VHDL VHDL HSIC Very High Speed Integrated Circuit 1981 IC ASIC 3 4 ASIC HDL ASIC 1983 VHDL 1985 VHDL 1986 7.2 ASIC VHDL 1986 IEEE VASG VHDL Analysis & Standardization Group 1987 5 LRM Language Reference Manual 12 IEEE Std 1076-1987 IEEE VHDL HDL 1989 VHDL VHDL EDA [7] 36

4-2 VHDL VHDL 3 RTL Behaviar ASIC FPGA ASIC 4-3 4-3-1 4.1 4.2 4.1 37

RTL 4-1 6 4.1 library ieee; use ieee.std_logic_1164.all; entity DFFR is port( CLK,RESET1,D : in std_logic; Q,QN :out std_logic ); end DFFR; architecture RTL of DFFR is signal Q_IN:std_logic; begin QN <= not Q_IN; Q <= Q_IN; process(clk,reset1)begin if(reset1='1')then Q_IN <= '0'; elsif(clk'event and CLK = '1')then Q_IN <= D; end if; end process; end RTL; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; 38

entity COUNTER is port( CLK,RESET : in std_logic; COUNT : out std_logic_vector(2 downto 0) ); end COUNTER; architecture RTL of COUNTER is component DFFR port(clk,reset1,d : in std_logic; Q,QN : out std_logic); end component; signal COUNT_IN_BAR : std_logic_vector(3 downto 0); signal COUNT_IN : std_logic_vector(2 downto 0); signal RESET_IN : std_logic; begin COUNT <= COUNT_IN; COUNT_IN_BAR(0) <= CLK; GEN1:for I in 0 to 2 generate U:DFFR port map( CLK => COUNT_IN_BAR(I), RESET1 => RESET_IN, D => COUNT_IN_BAR(I+1), Q => COUNT_IN(I), QN => COUNT_IN_BAR(I+1) ); end generate; 39

RESET_IN <= RESET or (COUNT_IN(1) and COUNT_IN(2)); end RTL; 4.2 library ieee; use ieee.std_logic_1164.all; use work.std.textio.all; use work.dffr; entity TESTBNCH is end TESTBNCH; architecture stimulus of TESTBNCH is component COUNTER is port ( ); CLK : in std_logic; RESET : in std_logic; COUNT : out std_logic_vector(2 downto 0) end component; signal CLK : std_logic; signal RESET : std_logic; signal COUNT : std_logic_vector(2 downto 0); begin DUT : COUNTER port map ( ); CLK, RESET, COUNT 40

CLOCK1:process begin CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns; end process CLOCK1; STIMULUS1 : process begin RESET <= '0'; wait for 5 ns; RESET <= '1'; wait for 10 ns; RESET <= '0'; wait for 180 ns; RESET <= '1'; wait for 20 ns; RESET <= '0'; wait; end process STIMULUS1; end stimulus; CLK COUNT 4.1 41

4-3-2 1 6 LED LED 7 7 3 7 3 COUNT A B C 3 7 START EN START EN 1,0 START EN 1,1 4.3 4.4 4.2 3 4.3 3 7 library ieee; use ieee.std_logic_1164.all; entity DECODER3TO7 is port ( A,B,C : in std_logic; START,EN : in std_logic; Y : out std_logic_vector(6 downto 0) ); end DECODER3TO7; architecture RTL of DECODER3TO7 is 42

signal INDATA : std_logic_vector(2 downto 0); begin INDATA <= C & B & A; process(indata,start,en)begin if(start = '1' and EN = '0')then --EN = STOP case INDATA is when "000" => Y <= "0001000"; --1 when "001" => Y <= "0010100"; --2 when "010" => Y <= "1001001"; --3 when "011" => Y <= "1010101"; --4 when "100" => Y <= "1011101"; --5 when "101" => Y <= "1110111"; --6 when others => Y <= "XXXXXXX"; --X end case; else null; --Y <= "1111111"; end if; end process; end RTL; 43

3 7 4.4 3 7 library ieee; use ieee.std_logic_1164.all; use std.textio.all; use work.decoder3to7; entity TESTBNCH is end TESTBNCH; architecture stimulus of TESTBNCH is component DECODER3TO7 is port ( A,B,C : in std_logic; START,EN : in std_logic; Y: out std_logic_vector(6 downto 0) ); end component; constant PERIOD: time := 100 ns; signal A,B,C : std_logic; signal START,EN : std_logic; signal Y: std_logic_vector(6 downto 0); signal done: boolean := false; begin DUT: DECODER3TO7 port map ( A,B,C, START,EN, Y ); STIMULUS1 : process begin 44

START <= '0';wait for 50 ns; START <= '1'; wait; end process STIMULUS1; STIMULUS2 : process begin EN <= '0'; wait for 245 ns; EN <= '1'; wait for 55 ns; EN <= '0'; wait for 333 ns; EN <= '1'; wait for 55 ns; EN <= '0'; wait for 300 ns; EN <= '1'; wait for 55 ns; end process STIMULUS2; STIMULUS3 : process begin A <= '0'; wait for 25 ns; A <= '1'; wait for 25 ns; end process STIMULUS3; STIMULUS4 : process begin B <= '0'; wait for 50 ns; B <= '1'; wait for 50 ns; B <= '0'; wait for 50 ns; 45

end process STIMULUS4; STIMULUS5 : process begin C <= '0'; wait for 100 ns; C <= '1'; wait for 50 ns; end process STIMULUS5; end stimulus; 4.2 4-3-3 4.1 4.3 4.5 4.6 4.3 CLK COUNT 3 START EN 1,0 COUNT A B C Y 7 46

START EN 1,1 START EN 1,0 DICE 4.1 4.3 VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; 4.5 entity DICE is port( CLK,RESET : in std_logic; Y : out std_logic_vector(6 downto 0); --COUNT : out std_logic_vector(2 downto 0); START,EN : in std_logic ); end DICE; architecture RTL of DICE is component COUNTER port ( CLK,RESET : in std_logic; COUNT : out std_logic_vector(2 downto 0) ); end component; 47

component DECODER3to7 port ( A,B,C : in std_logic; START,EN : in std_logic; Y : out std_logic_vector(6 downto 0) ); end component; signal U0_COUNT : std_logic_vector(2 downto 0); begin U0 : COUNTER port map ( CLK,RESET,U0_COUNT); U1 : DECODER3to7 port map ( U0_COUNT(0),U0_COUNT(1),U0_COUNT(2), START,EN, Y ); end RTL; 4.6 library ieee; use ieee.std_logic_1164.all; use std.textio.all; use work.dice; entity TESTBNCH is end TESTBNCH; architecture stimulus of TESTBNCH is component DICE is 48

port ( CLK,RESET : in std_logic; Y : out std_logic_vector(6 downto 0); --COUNT : out std_logic_vector(2 downto 0); START,EN : in std_logic ); end component; constant PERIOD: time := 100 ns; signal CLK,RESET : std_logic; signal Y : std_logic_vector(6 downto 0); --signal COUNT : std_logic_vector(2 downto 0); signal START,EN : std_logic; signal done : boolean := false; begin DUT: DICE port map ( CLK,RESET, Y,--COUNT, START,EN ); CLOCK1: process begin CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns; end process CLOCK1; STIMULUS1 : process begin 49

START <= '0'; wait for 20 ns; START <= '1'; wait; end process STIMULUS1; STIMULUS2 : process begin EN <= '0'; wait for 145 ns; EN <= '1'; wait for 35 ns; EN <= '0'; wait for 233 ns; EN <= '1'; wait for 35 ns; EN <= '0'; wait for 70 ns; EN <= '1'; wait for 35 ns; EN <= '0'; wait for 125 ns; EN <= '1'; wait for 35 ns; EN <= '0'; wait; end process STIMULUS2; STIMULUS3 : process begin RESET <= '0'; wait for 5 ns; RESET <= '1'; wait for 10 ns; RESET <= '0'; wait for 245 ns; RESET <= '1'; wait for 10 ns; RESET <= '0'; wait; end process STIMULUS3; end stimulus; 50

4.3 51

5 IC VHDL IC VHDL 3-7 VHDL VHDL VHDL VHDL 52

53

[1] [2] [3] [4] [5] [6] CQ [7] VHDL CQ 54

VHDL [7] 1 VHDL VHDL VHDL signal signal BBB std_logic_vector 4 downto 0 out out [7] 55

for-generate if-generate 2 for in generate end generate [ ] if generate end generate [ ] for-generate for-loop exit next If-generate TRUE If else [7] wait wait Wait wait until wait on wait on wait wait 1 [7] 1 wait 56

case case when = = If case 1 when others others 2 case [7] 2 case and or not and or nand nor xor 6 57

std_logic bit std_logic_vector Boolean C VHDL 2 and or xor [7] A = B and C and D and E A = B or C or D or E A = B xor C xor D xor E 2 AND-OR A = B nand C nand D nand E -- A = B and C or D and E -- not not and 58

59 2 AND-OR SEL 1 A SEL 0 B [7] VHDL architecture begin component [ ] [ ] end component architecture begin [7] port map port map 2 [7]