EDSF2008.ppt
|
|
|
- ちかこ くぬぎ
- 5 years ago
- Views:
Transcription
1 EDS fair 2008 SystemC/ANSI-C DesignPrototyper 1
2 DesignPrototyper USBlink IO Bridge( ) JPEG CODEC boost::serialization 2
3 DesignPrototyper 3
4 DesignPrototyper C/C++ Algorithm code C/C++ C/C++ Compiler SystemC(BCA), ANSI-C [FDA-C] DesignPrototyper TM Synthesizable Verilog HDL RTL Synthesis Net List SystemC Simulator HDL Simulator Hardware Accelerator ASIC/ FPGA Place and Route 4
5 5
6 6
7 DesignPrototyper DesignPrototyper RTL DSP 7
8 DesignPrototyper CPU,DSP SystemC/ANSI-C DesignPrototyper RTL DSP CPU 8
9 9
10 DesignPrototyper USBlink IO Bridge( ) JPEG CODEC boost::serialization 10
11 Configuration ASSP IP 11
12 Configuration ASSP IP 12
13 USBlink Hardware Block Diagram CY7C68013A SPARTAN3 i.mx MPU SD Controller SD_IN_FIFO EP0 GPIO FIFO Control AOUT0 AOUT1 AUDIO_OUT_FIFO AOUT2 EP_OUT FD[15:0] USB_IN_FIFO DATA[15:0] EP_IN USB_OUT_FIFO EP_LOCAL_OUT EP_LOCAL_IN GPIFADR[8:0] USBIF IO Bridge GPIO_LOCAL_IF RD WR CS CTL0 CTL1 CTL2 RDY0 RDY1 USBIF FIFO Control CPUIF Parameter registers AD[23:0] 13
14 14 USBlink hardware interface(ez-usb<->fpga) usbif_wr_n usbif_fd[15:0] usbif_fifo_full usbif_rd_n usbif_fifo_empty usbif_oe_n empty q[15:0] rd full data[15:0] wr usb_out_fifo usb_in_fifo usbif_sel_local_if usb_cmd_fifo usb_read_fifo USB IO Bridge empty q[15:0] rd full data[15:0] wr usbio_ad[15:0] usbio_wdata[15:0] usbio_rdata[15:0] usbio_wren usbio_rden CTL0 FD[15:0] RDY0 CTL2 CTL1 RDY1 usbio_cmd_full IFCLK usbio_empty PA0 PA1 PA2 usbif_clr_n PA3 EZ-USB FX2 wr data[15:0] rd q[15:0] wr data[15:0] full rd q[15:0] empty empty rd full FPGA Local bus
15 USBlink hardware interface (EZ-USB<->FPGA) Register write access(32bit address) Command format usb_cmd_fifo Single word 16bit data write func = 1000b length = 4 (fixed) func length address_l address_h wdata 15
16 USBlink hardware interface(ez-usb<->fpga) Register read access(32bit address) Command format Single word 16bit data read func = 1001b length = 4 (fixed) transfer_length = 2 (fixed) usb_cmd_fifo func length address_l address_h transfer_length usb_read_fifo rdata 16
17 USBlink IO Bridge SystemC BCA usblink_iobridge.cpp Target Device: spartan ns 100.0MHz) SystemC BCA RTL 6.49ns (154MHz)
18 USBlink IO Bridge, Target Device: 3s4000fg676-4 ISE i Slice Logic Utilization Number of Slice Flip Flops Number of 4 input LUTs Fmax Used ns ( MHz) Available
19 DesignPrototyper USBlink IO Bridge( ) JPEG CODEC boost::serialization 19
20 JPEG CODEC Altera Cyclone2 PWriteHuffmanCode COutBitStream dechuf_pattern_bank 0[63:0] dechuf_pattern_bank 1[63:0] CodeHuffman decode_getval DecodeHuffman CInBitStream decode_vlc Cyclone II EP2C50F -8 Total logic elements : 14,688 / 50,528 ( 29 % ) Total registers : 9436 Total memory bits : 43,776 / 594,432 ( 7 % ) Embedded Multiplier 9-bit elements : 42 / 172 ( 24 % ) FMAX MHz ( period = ns ) 20
21 Motion JPEG CODEC CCD FPGA Altera Cyclone2 Xilinx Spartan3, 21
22 = 2.56 M pixel 16 / M pixel/ = DCT M pixel/ 1MCU 16x16 Y Cb Cr 4 DCT 1 DCT 1 DCT 22
23 JPEG CODEC JPEG JPEG JPEG RGB YCbCr Huffman DCT idct YCbCr RGB JPEG 23
24 JPEG C++, ISBN JPEG C ,800 ISBN
25 JPEG CODEC ( ) SourceMonitor Version 2.3(*) SystemC RTL statements SystemC statements RTL statements Verilog HDL statements( ) (*) Campwood Software 25
26 JPEG CODEC ( ) Compilation Hierarchy Node Memory Bits DSP 18x18 SystemC Verilog SystemC Verilog JPEGencoderCore [DUT] Huffman [p_huffman] BCA COutBitStream [p_coutbitstream] BCA CodeHuffman [p_codehuffman] BCA PWriteHuffmanCode [p_pwritehuffmancode] FIFO huffman_fifo [p_huffman_fifo] FIFO scfifo_10x64 [p_setbyte_fifo] FIFO setbits_fifo [p_setbits_fifo] RTL JPEGavalonSlaveIF [p_jpegavalonslaveif] BCA JPEGcnt [p_jpegcnt] JPEGdec [p_jpegdec] 4558 BCA DecodeHuffman [p_decodehuffman] BCA DinBitStream [p_dinbitstream] RTL decode_getval [p_decode_getval] RTL decode_vlc [p_decode_vlc] BCA JPEGmcubufTest [p_jpegmcubuftest] JPEGpre [p_jpegpre] 0 DCT2d [p_jpegdct2d] BCA DCT2dDataIn [p_dct2ddatain] BCA DCT2dReadMatrix [p_dct2dreadmatrix] RTL dct2d_din_sel [p_dct2d_din_sel] RTL dct2d_dout [p_dct2d_dout] RTL dct2d_rotate_matrix [p_dct2d_rotate_matrix] RTL dct8 [p_dct8] JPEGquant [p_jpegquant] RTL JPEGiquant_select_pattern [p_jpegiquant_select_pattern] BCA JPEGquantCnt [p_jpegquantcnt] RTL JPEGquantDataOut [p_jpegquantdataout] 24 0 BCA JPEGquantGenPattern [p_jpegquantgenpattern] RTL JPEGquantMult [p_jpegquantmult] ROM mquantumt_wrapper [p_mquantumt] SRAM mdctdatay_wrapper [p_mdctdatay] RTL jpeg_sync_level [p_mcucnt_done_sync] ROM mjpegheadert_wrapper [p_mjpegheadert] SRAM mquantdatap_wrapper [p_mquantdatap] SRAM mtrace_wrapper [p_mtrace_wrapper] Total Total(Statements) Total(Lines)
27 JPEG Huffman FIFO JPEG 8 bit x 623 RAM 27
28 JPEG JPEG CODEC ( ) Huffman Lookup table DCT/IDCT / JPEG 28
29 JPEG CPU CPU Huffman 29
30 DCT/iDCT DCT/iDCT Chen 18bit x 18bit DCT/iDCT DCT/iDCT X,Y 30
31 31 DCT/iDCT x0 x1 x2 x3 x4 x5 x6 x7 en_in
32 JPEG Huffman JPEG, JPEG 32
33 SystemC BCA JPEGcnt.cpp 33
34 DesignPrototyper USBlink IO Bridge( ) JPEG CODEC boost::serialization 34
35 35 / OS C++ SystemC Verilog to C++ /
36 Verilog HDL to C++ Translator Verilator Verilog HDL Verilog HDL C++/SystemC Wilson Snyder, Paul Wasson and Duane Galbi GPL 36
37 Verilog HDL to C++ Translator Verilator Do not download this program if you are expecting a full featured replacement for NC-Verilog, VCS or another commercial Verilog simulator for a little project! Don't get it if you expect a corporate support organization. However, if you are looking for a path to migrate synthesizable Verilog to C++ or SystemC, and writing just a touch of C code and Makefiles doesn't scare you off, this is the free Verilog compiler for you. 37
38 Verilator SystemC Verilog HDL Verilog HDL SystemC Verilog HDL RTL Initial,Task Verilog HDL IP SystemC (SRAM,ROM,FIFO ) HDL 38
39 Verilator Verilog HDL SystemC Verilator Verilog HDL SystemC % verilator.csh --sc Rotation.v a[15:0] b[15:0] to_uint32t<16> Verirator SystemC RTL rotation_cs start start rotation_we clk reset to_uint32t<16> a b Rotation vrotation clk reset rotation_ad from_uint32t<18> rotation_ad[17:0] rotation_we./obj_dir/vrotation.h./obj_dir/vrotation.cpp./obj_dir/rotation.h./obj_dir/rotation.cpp Velirator SystemC 2bit 32bit uint32_t bit Rotation,SystemC 39
40 JPEG JPEG CODEC RTL SystemC BCA ANSI-C JPEG code SystemC simulation model stimulus FIFO JPEGencoderCore Avalon BUS model DUT MCU Buffer SRAM 40
41 JPEG iprove JPEG CODEC FPGA JPEG CODEC Virtex2 SystemC BCA ANSI-C JPEG code SystemC simulation model stimulus FIFO JPEGencoderCore_proxy Avalon BUS model DUT JPEGencoderCore Device Utilization Summary: Number of MULT18X18s 21 out of % Number of RAMB16s 16 out of 168 9% Number of SLICEs out of % Number of TBUFs 447 out of % MCU Buffer SRAM 41
42 JPEG SystemC /Verilog RTL/ (ANSI-C) 42
43 Garden 352x240 Container 352x288 Hall monitor 352x288 CIPR SIF Sequences 43
44 PC Intel(R) Pentium(R) 4 CPU 2.53GHz OS CentOS EL DesignPrototyper Version 3.5.2c C++ gcc (GCC) (Red Hat Linux ) SystemC OSCI Verilog SystemC Verilator Verilog HDL ModelSIM AE 6.1g 44
45 iprove SystemC p_jpegencodercore p_jpegencodercore_proxy 45
46 SystemC/Verilator SystemC/Verilator PLI BCA RTL Verilog HDL 46
47 iprove FPGA FPGA iprove SystemC/HDL iprove FPGA 47
48 DesignPrototyper USBlink IO Bridge( ) JPEG CODEC boost::serialization 48
49 Top Down Algorithm code C/C++ C/C++ Compiler SystemC(BCA), ANSI-C [FDA-C] DesignPrototyper TM Synthesizable Verilog HDL RTL Synthesis Net List SystemC Simulator HDL Simulator Hardware Accelerator ASIC/ FPGA Place and Route 49
50 Top Down C/C++ SystemC SystemC SystemC BCA / / 50
51 boost::serialization / C/C++ A B C A B C SystemC SystemC BCA 51
52 H.264 x264 - a free h264/avc encoder GNU General Public License 52
53 H.264 Target Device: Virtex ns 105.2MHz) DSP SystemC BCA RTL DSP /64 10ns (100MHz) / 53
54 H.264, Target Device: xc4vlx25-10ff668 ISE i Slice Logic Utilization Used Available Utilization Number of Slice Flip Flops ,504 3% Number of 4 input LUTs 2,247 21,504 10% Fmax 9.997ns ( M Hz) 54
55 boost::serialization boost:: serialization C++ Boost Input/Output Boost Software License BSD : boost::serialization 55
56 C++ Boost Web 56
57 (1/3) H264_DCT8x8_t.h #ifndef _H264_DCT8x8_t_H #define _H264_DCT8x8_t_H 1 #include <stdint.h> #ifdef cplusplus extern "C" { #endif void h264_dct8x8_set_mode( int _cmode ) ; void h264_dct8x8_dump( int16_t dct[4][4][4], uint8_t *pix1, uint8_t *pix2, int fenc_strid, int fdec_strid ) ; #ifdef cplusplus } #endif #ifdef cplusplus #include <string> #include <fstream> #include <boost/archive/text_oarchive.hpp> #include <boost/archive/text_iarchive.hpp> #include <boost/serialization/string.hpp> } #endif class H264_DCT8x8_t { public: /// int record ; int cmode ; uint8_t mpix1[8][8] ; uint8_t mpix2[8][8] ; int16_t mdct8x8_ref[8][8] ; private: friend class boost::serialization::access ; /// template<class Archive> void serialize(archive& ar, const unsigned int version) { ar & record ; ar & cmode ; ar & mpix1 ; ar & mpix2 ; ar & mdct8x8_ref ; } 57
58 (2/3) H264_DCT8x8_t.h #include "H264_dump.h" int fx( int pos, int k ) { return ( pos & 0x01 ) << 2 ( k & 0x03 ) ; } int fy( int pos, int k ) { return ( pos & 0x02 ) << 1 ( k & 0x0c ) << 2 ; } int fix( int pos, int ix ) { return ( pos & 0x01 ) << 2 ix ; } int fiy( int pos, int iy ) { return ( pos & 0x02 ) << 1 iy ; } void dump_block_n( char *message, int n,uint8_t *v, int stride ) { int x, y ; int gl_dump_level = 1 ; if ( gl_dump_level >= 1 ) { fprintf( stderr, "%s stride=%d n", message, stride ) ; for ( y = 0 ; y < n ; y++ ) { fprintf( stderr, "%s y=%d [", message, y ) ; for ( x = 0 ; x < n ; x++ ) { fprintf( stderr, "%6d", v[x+ y * stride ] ) ; } fprintf( stderr, "] n" ) ; } } } 58
59 (3/3) /// ( ) H264_DCT8x8_t() { ; } /// ( ) H264_DCT8x8_t( int _record, int _cmode, int16_t dct[4][4][4], uint8_t *pix1, uint8_t *pix2, int fenc_strid, int fdec_strid ) { int pos ; record = _record ; cmode = _cmode ; for ( int iy = 0 ; iy < 8 ; iy++ ) { for ( int ix = 0 ; ix < 8 ; ix++ ) { mpix1[iy][ix] = pix1[ix + fenc_strid * iy] ; mpix2[iy][ix] = pix2[ix + fdec_strid * iy] ; } } for ( pos = 0 ; pos < 4 ; pos++ ) { for ( int iy = 0 ; iy < 4 ; iy++ ) { for ( int ix = 0 ; ix < 4 ; ix++ ) { mdct8x8_ref[fiy(pos,iy)][fix(pos,ix)] = dct[pos][iy][ix] ; } } } DEBUG_fprintf( stderr, "fenc_strid=%d fdec_strid=%d n", fenc_strid, fdec_strid ) ; DEBUG_fprintf( stderr, "record=%d n", record ) ; dump_block( "H264_DCT8x8_t::mPIX1", mpix1 ) ; dump_block( "H264_DCT8x8_t::mPIX2", mpix2 ) ; dump_block_n( "H264_DCT8x8_t::pix1", 8, pix1, fenc_strid ) ; dump_block_n( "H264_DCT8x8_t::pix2", 8, pix2, fdec_strid ) ; dump_block( "H264_DCT8x8_t::mDCT8x8_REF", mdct8x8_ref } } ; #endif // cplusplus #endif // _H264_DCT8x8_t_H 59
60 ./common/dct.c x264 #include "../debug/h264_dct8x8_t.h" static void sub8x8_dct( int16_t dct[4][4][4], uint8_t *pix1, uint8_t *pix2 ) { sub4x4_dct( dct[0], &pix1[0], &pix2[0] ); sub4x4_dct( dct[1], &pix1[4], &pix2[4] ); sub4x4_dct( dct[2], &pix1[4*fenc_stride+0], &pix2[4*fdec_stride+0] ); sub4x4_dct( dct[3], &pix1[4*fenc_stride+4], &pix2[4*fdec_stride+4] ); // h264_dct8x8_dump( dct, pix1, pix2, FENC_STRIDE, FDEC_STRIDE ) ; } 60
61 DCT8x8_stimulus.h H.264 Stimulus ( ) #ifndef _DCT8x8_stimulus_H #define _DCT8x8_stimulus_H #include <systemc.h> #include <cstdio> #include "my_debug.h" #include "H264_cqm_t.h" #include "H264_DCT8x8_t.h" #include "H264_DCT8x8_quant_t.h" SC_MODULE(DCT8x8_stimulus) { sc_in_clk clk; sc_out<bool> reset;. private: std::ifstream *iop_h264_cqm ; std::ifstream *iop_h264_dct8x8 ; std::ifstream *iop_h264_dct8x8_quant ; H264_cqm_t u_h264_cqm ; H264_DCT8x8_t u_h264_dct8x8 ; H264_DCT8x8_quant_t u_h264_dct8x8_quant ; 61
62 DCT8x8_stimulus.cpp H.264 Stimulus ( ) #include "DCT8x8_stimulus.h" #define U_H264_DCT8x8 u_h264_dct8x8_quant void DCT8x8_stimulus::entity() { int i ; bool bank ; uint32_t cmode ; // iop_h264_cqm = new std::ifstream("h264_cqm.in" ) ; iop_h264_dct8x8 = new std::ifstream("h264_dct8x8.in") iop_h264_dct8x8_quant = new std::ifstream("h264_dct8x8_quant.in" ) ; 62
63 H.264 Stimulus ( ) DCT8x8_stimulus.cpp void DCT8x8_stimulus::load_data( uint32_t *mode ) { boost::archive::text_iarchive ia( *iop_h264_dct8x8 ) ; ia >> u_h264_dct8x8 ; *mode = u_h264_dct8x8.cmode ; DEBUG_fprintf( stdout, "u_h264_dct8x8.cmode=%d mode=%u n", u_h264_dct8x8.cmode, *mode ) ; dump_block( "u_h264_dct8x8.mpix1", u_h264_dct8x8.mpix1 ) ; dump_block( "u_h264_dct8x8.mpix2", u_h264_dct8x8.mpix2 ) ; dump_block( "u_h264_dct8x8.mdct8x8_ref", u_h264_dct8x8.mdct8x8_ref ) ; } 63
64 DCT8x8_stimulus.cpp H.264 Stimulus ( ) void DCT8x8_stimulus::mPIX1_write( bool bank, uint32_t iy ) { unsigned int ad = ( bank << 4 ) iy << 1 ; wait() ; mpix1_wraddress.write( ad ) ; mpix1_data0.write( u_h264_dct8x8.mpix1[iy][0] ) ; mpix1_data1.write( u_h264_dct8x8.mpix1[iy][1] ) ; mpix1_data2.write( u_h264_dct8x8.mpix1[iy][2] ) ; mpix1_data3.write( u_h264_dct8x8.mpix1[iy][3] ) ; mpix1_wren.write( true ) ; wait() ; mpix1_wren.write( false ) ; wait() ; ad++ ; mpix1_wraddress.write( ad ) ; mpix1_data0.write( u_h264_dct8x8.mpix1[iy][4] ) ; mpix1_data1.write( u_h264_dct8x8.mpix1[iy][5] ) ; mpix1_data2.write( u_h264_dct8x8.mpix1[iy][6] ) ; mpix1_data3.write( u_h264_dct8x8.mpix1[iy][7] ) ; mpix1_wren.write( true ) ; wait() ; mpix1_wren.write( false ) ; wait() ; } 64
65 H.264 Stimulus( ) DCT8x8_stimulus.cpp wait_until( dct8x8_done.delayed() == true ) ; time_done = sc_simulation_time() ; for( int iy = 0 ; iy < 8 ; iy++ ) { mdct8x8_read( bank, iy ) ; } int unmatch_count = compare_block( "mdct8x8 vs u_h264_dct8x8.mdct8x8_ref", mdct8x8, u_h264_dct8x8.mdct8x8_ref ) ; if ( unmatch_count == 0 ) { DEBUG_fprintf( stdout, "MATCH compare_block count=%d n", unmatch_count ) ; } else { unmatch_run++ ; DEBUG_fprintf( stdout, "UNMATCH compare_block count=%d unmatch_run=%d n", unmatch_count, unmatch_run ) ; } 65
66 Boost::serialization script, ESL SystemC HDL (C/C++/PLI,VPI,DPI,FLI) Missing-link 66
67 DesignPrototyper USBlink IO Bridge( ) JPEG CODEC boost::serialization 67
68 , 68
69 69 DesignPrototyper ANSI-C/SystemC RTL SystemC BCA( ) (IP ) DesignPrototyper
70 70
71 71
72 72
EDSF2006_ PDF
/SystemC SystemC FPFA 1 Techno Repo LSI / 2 Techno Repo 3 Techno Repo 4 Techno Repo DesignPrototyper 5 Techno Repo 6 Techno Repo 7 Techno Repo 8 Techno Repo 9 Techno Repo C/C++ C/C++/SystemC IP (Verilog-HDL/
SystemC 2.0を用いた簡易CPUバスモデルの設計
SystemC 2.0 CPU CPU CTD&SW CT-PF 2002/1/23 1 CPU BCA UTF GenericCPU IO (sc_main) 2002/1/23 2 CPU CPU CQ 1997 11 Page 207 4 Perl Verilog-HDL CPU / Verilog-HDL SystemC 2.0 (asm) ROM (test.hex) 2002/1/23
SystemC言語概論
SystemC CPU S/W 2004/01/29 4 SystemC 1 SystemC 2.0.1 CPU S/W 3 ISS SystemC Co-Simulation 2004/01/29 4 SystemC 2 ISS SystemC Co-Simulation GenericCPU_Base ( ) GenericCPU_ISS GenericCPU_Prog GenericCPU_CoSim
Nios® II HAL API を使用したソフトウェア・サンプル集 「Modular Scatter-Gather DMA Core」
ALTIMA Company, MACNICA, Inc Nios II HAL API Modular Scatter-Gather DMA Core Ver.17.1 2018 8 Rev.1 Nios II HAL API Modular Scatter-Gather DMA Core...3...3...4... 4... 5 3-2-1. msgdma... 6 3-2-2. On-Chip
XAPP858 - High-Performance DDR2 SDRAM Interface In Virtex-5 Devices
XAPP858 (v1.1) 2007 1 9 : Virtex-5 FPGA Virtex-5 DDR2 SDRAM : Karthi Palanisamy Maria George (v1.1) DDR2 SDRAM Virtex -5 I/O ISERDES (Input Serializer/Deserializer) ODDR (Output Double Data Rate) DDR2
デザインパフォーマンス向上のためのHDLコーディング法
WP231 (1.1) 2006 1 6 HDL FPGA TL TL 100MHz 400MHz HDL FPGA FPGA 2005 2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx,
untitled
13 Verilog HDL 16 CPU CPU IP 16 1023 2 reg[ msb: lsb] [ ]; reg [15:0] MEM [0:1023]; //16 1024 16 1 16 2 FF 1 address 8 64 `resetall `timescale 1ns/10ps module mem8(address, readdata,writedata, write, read);
プロセッサ・アーキテクチャ
2. NII51002-8.0.0 Nios II Nios II Nios II 2-3 2-4 2-4 2-6 2-7 2-9 I/O 2-18 JTAG Nios II ISA ISA Nios II Nios II Nios II 2 1 Nios II Altera Corporation 2 1 2 1. Nios II Nios II Processor Core JTAG interface
とても使いやすい Boost の serialization
とても使いやすい Boost の serialization Zegrahm シリアライズ ( 直列化 ) シリアライズ ( 直列化 ) とは何か? オブジェクトデータをバイト列や XML フォーマットに変換すること もう少しわかりやすく表現すると オブジェクトの状態を表す変数 ( フィールド ) とオブジェクトの種類を表す何らかの識別子をファイル化出来るようなバイト列 XML フォーマット形式で書き出す事を言う
strtok-count.eps
IoT FPGA 2016/12/1 IoT FPGA 200MHz 32 ASCII PCI Express FPGA OpenCL (Volvox) Volvox CPU 10 1 IoT (Internet of Things) 2020 208 [1] IoT IoT HTTP JSON ( Python Ruby) IoT IoT IoT (Hadoop [2] ) AI (Artificial
PLDとFPGA
PLDFPGA 2002/12 PLDFPGA PLD:Programmable Logic Device FPGA:Field Programmable Gate Array Field: Gate Array: LSI MPGA:Mask Programmable Gate Array» FPGA:»» 2 FPGA FPGALSI FPGA FPGA Altera, Xilinx FPGA DVD
非圧縮の1080p60ビデオをサポートする3Gbps SDIコネクティビティ･ソリューション
LMH0340,LMH0341 Literature Number: JAJA432 SIGNAL PATH designer Tips, tricks, and techniques from the analog signal-path experts No. 113... 1-5...4... 7 1080p60 3Gbps SDI Mark Sauerwald, SDI Applications
Nios II ハードウェア・チュートリアル
Nios II ver. 7.1 2007 8 1. Nios II FPGA Nios II Quaruts II 7.1 Nios II 7.1 Nios II Cyclone II count_binary 2. 2-1. http://www.altera.com/literature/lit-nio2.jsp 2-2. Nios II Quartus II FEATURE Nios II
1 1 2 2 2-1 2 2-2 4 2-3 11 2-4 12 2-5 14 3 16 3-1 16 3-2 18 3-3 22 4 35 4-1 VHDL 35 4-2 VHDL 37 4-3 VHDL 37 4-3-1 37 4-3-2 42 i
1030195 15 2 10 1 1 2 2 2-1 2 2-2 4 2-3 11 2-4 12 2-5 14 3 16 3-1 16 3-2 18 3-3 22 4 35 4-1 VHDL 35 4-2 VHDL 37 4-3 VHDL 37 4-3-1 37 4-3-2 42 i 4-3-3 47 5 52 53 54 55 ii 1 VHDL IC VHDL 5 2 3 IC 4 5 1 2
RX600 & RX200シリーズ アプリケーションノート RX用仮想EEPROM
R01AN0724JU0170 Rev.1.70 MCU EEPROM RX MCU 1 RX MCU EEPROM VEE VEE API MCU MCU API RX621 RX62N RX62T RX62G RX630 RX631 RX63N RX63T RX210 R01AN0724JU0170 Rev.1.70 Page 1 of 33 1.... 3 1.1... 3 1.2... 3
1
PalmGauss SC PGSC-5G Instruction Manual PalmGauss SC PGSC-5G Version 1.01 PalmGauss SC PGSC5G 1.... 3 2.... 3 3.... 3 3.1... 3 3.2... 3 3.3 PalmGauss... 4 3.4... 4 3.4.1 (Fig. 4)... 4 3.4.2 (Fig. 5)...
HyRAL®FPGA設計仕様書
HyRAL Encryption FPGA HyRAL FPGA 2009/12/ 13 2 2010/01/11 3. FPGA 3.1. Const1, 2,3 3.3.ciphergen 3.3.6. 3.4. Decrypt 4 3 2010/01/26 1. i 1.... 1 2.... 1 2.1. FPGA... 1 2.2.... 1 2.3.... 1 2.4. IP... 1
cpp1.dvi
2017 c 1 C++ (1) C C++, C++, C 11, 12 13 (1) 14 (2) 11 1 n C++ //, [List 11] 1: #include // C 2: 3: int main(void) { 4: std::cout
RX600 & RX200シリーズ RX用シンプルフラッシュAPI アプリケーションノート
R01AN0544JU0240 Rev.2.40 RX600 RX200 API MCU API API RX 0xFF 3.10 API RX610 RX621 RX62N RX62T RX62G RX630 RX631 RX63N RX63T RX210 1.... 2 2. API... 3 3.... 11 4.... 16 5. API... 18 6.... 32 R01AN0544JU0240
/ / SeamlessCVE
/ / SeamlessCVE From ASIC to SoC Original Hardware Content CPU Core Memory DSP Core Glue Logic PCI Controller Original Hardware Content USB Controller USART Slide 2 SoC SoC ASIC System Architecture ASIC
26 FPGA 11 05340 1 FPGA (Field Programmable Gate Array) ASIC (Application Specific Integrated Circuit) FPGA FPGA FPGA FPGA Linux FreeDOS skewed way L1
FPGA 272 11 05340 26 FPGA 11 05340 1 FPGA (Field Programmable Gate Array) ASIC (Application Specific Integrated Circuit) FPGA FPGA FPGA FPGA Linux FreeDOS skewed way L1 FPGA skewed L2 FPGA skewed Linux
組込みシステムシンポジウム2011 Embedded Systems Symposium 2011 ESS /10/20 FPGA Android Android Java FPGA Java FPGA Dalvik VM Intel Atom FPGA PCI Express DM
Android Android Java Java Dalvik VM Intel Atom PCI Express DMA 1.25 Gbps Atom Android Java Acceleration with an Accelerator in an Android Mobile Terminal Keisuke Koike, Atsushi Ohta, Kohta Ohshima, Kaori
Nios II 簡易チュートリアル
Nios II Ver. 7.1 2007 10 1. Nios II Nios II JTAG UART LED 8 PIO LED < > Quartus II SOPC Builder Nios II Quartus II.sof Nios II IDE Stratix II 2S60 RoHS Nios II Quartus II http://www.altera.com/literature/lit-nio2.jsp
「FPGAを用いたプロセッサ検証システムの製作」
FPGA 2210010149-5 2005 2 21 RISC Verilog-HDL FPGA (celoxica RC100 ) LSI LSI HDL CAD HDL 3 HDL FPGA MPU i 1. 1 2. 3 2.1 HDL FPGA 3 2.2 5 2.3 6 2.3.1 FPGA 6 2.3.2 Flash Memory 6 2.3.3 Flash Memory 7 2.3.4
SCV in User Forum Japan 2003
Open SystemC Initiative (OSCI) SystemC - The SystemC Verification Standard (SCV) - Stuart Swan & Cadence Design Systems, Inc. Q0 Q1 Q2 Q3 Q4 Q5 2 SystemC Q0 Q1 Q2 Q3 Q4 Q5 3 Verification Working Group
matrox0
Image processing products Hardware/Software Software Hardware INDEX 4 3 2 12 13 15 18 14 11 10 21 26 20 9 8 7 6 5 Hardware 2 MatroxRadient 3 MatroxSolios MatroxMorphis MatroxVio 10 MatroxOrionHD 11 MatroxConcord
新コンフィギュレータのフレームワークについて
: 2007 12 7 6: 2009 5 9 TOPPERS 1.... 4 1.1... 4 1.2 TOPPERS... 4 2.... 4 2.1... 4 3.... 8 4.... 9 4.1... 9 4.2... 10 4.3... 10 4.3.1... 11 4.3.2 INCLUDE... 11 4.3.3 C... 12 4.4 API... 14 4.2.1 API...
WinDriver PCI Quick Start Guide
WinDriver PCI/PCI Express/PCMCIA 5! WinDriver (1) DriverWizard (2) DriverWizard WinDriver (1) Windows 98/Me/2000/XP/Server 2003/Vista Windows CE.NET Windows Embedded CE v6.00 Windows Mobile 5.0/6.0 Linux
Smalltalk_
DLLCC VisualWorks C Mac OS SSK-LampControl/ VisualWorksWithJun SSK-LampControl.h include SSK SSK FileBrowser SSK-LampControl.st FIle in SSK-LampControl File in SSK File in ( Smalltalk.SSK) ( C ) Controller
MINI2440マニュアル
ARM Cortex-M3 STM32F103 (GCC TOPPERS/ASP ) http://www.nissin-tech.com info@nissin-tech.com 2009/10/15 copyright@2009 1 STM32F103...3 STM32...4...8 3.1...8 3.2...9 3.3...13 KEIL...19 4.1 KEIL...19 4.2...22
Microsoft PowerPoint - Lec pptx
Course number: CSC.T34 コンピュータ論理設計 Computer Logic Design 5. リコンフィギャラブルシステム Reconfigurable Systems 吉瀬謙二情報工学系 Kenji Kise, Department of Computer Science kise _at_ c.titech.ac.jp www.arch.cs.titech.ac.jp/lecture/cld/
64bit SSE2 SSE2 FPU Visual C++ 64bit Inline Assembler 4 FPU SSE2 4.1 FPU Control Word FPU 16bit R R R IC RC(2) PC(2) R R PM UM OM ZM DM IM R: reserved
(Version: 2013/5/16) Intel CPU (kashi@waseda.jp) 1 Intel CPU( AMD CPU) 64bit SIMD Inline Assemler Windows Visual C++ Linux gcc 2 FPU SSE2 Intel CPU double 8087 FPU (floating point number processing unit)
Condition DAQ condition condition 2 3 XML key value
Condition DAQ condition 2009 6 10 2009 7 2 2009 7 3 2010 8 3 1 2 2 condition 2 3 XML key value 3 4 4 4.1............................. 5 4.2...................... 5 5 6 6 Makefile 7 7 9 7.1 Condition.h.............................
(Version: 2017/4/18) Intel CPU 1 Intel CPU( AMD CPU) 64bit SIMD Inline Assemler Windows Visual C++ Linux gcc 2 FPU SSE2 Intel CPU do
(Version: 2017/4/18) Intel CPU (kashi@waseda.jp) 1 Intel CPU( AMD CPU) 64bit SIMD Inline Assemler Windows Visual C++ Linux gcc 2 FPU SSE2 Intel CPU double 8087 FPU (floating point number processing unit)
VLD Kazutoshi Kobayashi
VLD Kazutoshi Kobayashi (kobayasi@kuee.kyoto-u.ac.jp) 2005 8 26-29 1, Verilog-HDL, Verilog-HDL. Verilog-HDL,, FPGA,, HDL,. 1.1, 1. (a) (b) (c) FPGA (d). 2. 10,, Verilog-HDL, FPGA,. 1.2,,,, html. % netscape
HardCopy IIIデバイスの外部メモリ・インタフェース
7. HardCopy III HIII51007-1.0 Stratix III I/O HardCopy III I/O R3 R2 R SRAM RII+ RII SRAM RLRAM II R HardCopy III Stratix III LL elay- Locked Loop PLL Phase-Locked Loop On-Chip Termination HR 4 36 HardCopy
Copyright Oracle Parkway, Redwood City, CA U.S. GOVERNMENT END USERS: Oracle programs, including any operating system, integrated softw
Oracle Solaris Studio 12.3 Part No: E26466 2011 12 Copyright 2011 500 Oracle Parkway, Redwood City, CA 94065 U.S. GOVERNMENT END USERS: Oracle programs, including any operating system, integrated software,
Power Calculator
1 4... 4... 4... 5 6... 6... 6 isplever... 6... 7... 8... 8... 8 (NCD)... 9 (.vcd)... 10... 11...11... 12 Power Summary... 16 Logic Block... 19 Clocks... 20 I/O... 20 I/O Term... 21 Block RAM... 22 DSP...
Stratix IIIデバイスの外部メモリ・インタフェース
8. Stratix III SIII51008-1.1 Stratix III I/O R3 SRAM R2 SRAM R SRAM RII+ SRAM RII SRAM RLRAM II 400 MHz R Stratix III I/O On-Chip Termination OCT / HR 4 36 R ouble ata RateStratix III FPGA Stratix III
main.dvi
CAD 2001 12 1 1, Verilog-HDL, Verilog-HDL. Verilog-HDL,, FPGA,, HDL,. 1.1, 1. (a) (b) (c) FPGA (d). 2. 10,, Verilog-HDL, FPGA,. 1.2,,,, html. % netscape ref0177/html/index.html.,, View Encoding Japanese
quattro.PDF
Quattro USB Audio Interface 2 M-AUDIO 3 Windows Windows 98 SE/ Windows ME/ Windows 2000/ Windows XP Platinum III 500MHz/ 96kHz Platinum II 400MKz/ 48kHz 128MB RAM / 96kHz 64MB RAM/ 48kHz Macintosh USB
double float
2015 3 13 1 2 2 3 2.1.......................... 3 2.2............................. 3 3 4 3.1............................... 4 3.2 double float......................... 5 3.3 main.......................
2008 DS T050049
DS T050049. PSP DS DS DS RPG DS OS Windows XP DevkiPro OS DS CPU ARM devkitarm MSYS MinGW MSYS MinGW Unix OS C++ C++ make nds nds DS DS micro SD Card nds DS DS DS nds C Java C++ nds nds DS 2008 DS T050049
untitled
FutureNet Microsoft Corporation Microsoft Windows Windows 95 Windows 98 Windows NT4.0 Windows 2000, Windows XP, Microsoft Internet Exproler (1) (2) (3) COM. (4) (5) ii ... 1 1.1... 1 1.2... 3 1.3... 6...
untitled
II yacc 005 : 1, 1 1 1 %{ int lineno=0; 3 int wordno=0; 4 int charno=0; 5 6 %} 7 8 %% 9 [ \t]+ { charno+=strlen(yytext); } 10 "\n" { lineno++; charno++; } 11 [^ \t\n]+ { wordno++; charno+=strlen(yytext);}
A Responsive Processor for Parallel/Distributed Real-time Processing
E-mail: yamasaki@{ics.keio.ac.jp, etl.go.jp} http://www.ny.ics.keio.ac.jp etc. CPU) I/O I/O or Home Automation, Factory Automation, (SPARC) (SDRAM I/F, DMAC, PCI, USB, Timers/Counters, SIO, PIO, )
? FPGA FPGA FPGA : : : ? ( ) (FFT) ( ) (Localization) ? : 0. 1 2 3 0. 4 5 6 7 3 8 6 1 5 4 9 2 0. 0 5 6 0 8 8 ( ) ? : LU Ax = b LU : Ax = 211 410 221 x 1 x 2 x 3 = 1 0 0 21 1 2 1 0 0 1 2 x = LUx = b 1 31
thesis.dvi
H8 e041220 2009 2 Copyright c 2009 by Kentarou Nagashima c 2009 Kentarou Nagashima All rights reserved , H8.,,,..,.,., AKI-H8/3052LAN. OS. OS H8 Write Turbo. H8 C, Cygwin.,., windows. UDP., (TA7279P).,.
- - http://168iroha.net 018 10 14 i 1 1 1.1.................................................... 1 1.................................................... 7.1................................................
VHDL
VHDL 1030192 15 2 10 1 1 2 2 2.1 2 2.2 5 2.3 11 2.3.1 12 2.3.2 12 2.4 12 2.4.1 12 2.4.2 13 2.5 13 2.5.1 13 2.5.2 14 2.6 15 2.6.1 15 2.6.2 16 3 IC 17 3.1 IC 17 3.2 T T L 17 3.3 C M O S 20 3.4 21 i 3.5 21
解きながら学ぶC++入門編
!... 38!=... 35 "... 112 " "... 311 " "... 4, 264 #... 371 #define... 126, 371 #endif... 369 #if... 369 #ifndef... 369 #include... 3, 311 #undef... 371 %... 17, 18 %=... 85 &... 222 &... 203 &&... 40 &=...
, FPGA Verilog-HDL
Kazutoshi Kobayashi (kobayasi@kuee.kyoto-u.ac.jp) 2007 12 19-20 1 1 1.1...................................... 1 1.2,................................. 1 2 2 2.1 FPGA......................... 2 2.2 Verilog-HDL.............................
テストコスト抑制のための技術課題－DFTとATEの観点から
2 -at -talk -talk -drop 3 4 5 6 7 Year of Production 2003 2004 2005 2006 2007 2008 Embedded Cores Standardization of core Standard format Standard format Standard format Extension to Extension to test
LSI A B C D CPU for i=0; i Lab GPIO_35 GPIO
6,GPIO, PSoC 3/5 GPIO HW Polling and Interrupt PSoC Experiment Lab PSoC 3/5 GPIO Experiment Course Material 6 V2.02 October 15th. 2012 GPIO_35.PPT (65 Slides) Renji Mikami Renji_Mikami@nifty.com Lab GPIO_35
Kazutoshi Kobayashi (kobayasi kit.ac.jp)
Kazutoshi Kobayashi (kobayasi kit.ac.jp) 2009 11 24-25 1 1 1.1.................................. 1 1.2,............................ 1 2 2 2.1 FPGA.................... 2 2.2 Verilog-HDL........................
untitled
FPGA SATA AE/ AVNET, INC. : 1921 : 1955 / : 1960 NYSE - AVT ( Sector : Technology ) CEO: Roy Vallee ( : : : 11,000 : KPMG LLP : 6 30 Fortune 500 ( 2006 212 ) InformationWeek 500 ( 2004 3 ) Fortune Top50
ネットリストおよびフィジカル・シンセシスの最適化
11. QII52007-7.1.0 Quartus II Quartus II atom atom Electronic Design Interchange Format (.edf) Verilog Quartus (.vqm) Quartus II Quartus II Quartus II Quartus II 1 Quartus II Quartus II 11 3 11 12 Altera
FreeBSD 1
FreeBSD 1 UNIX OS 1 ( ) open, close, read, write, ioctl (cdevsw) OS DMA 2 (8 ) (24 ) 256 open/close/read/write Ioctl 3 2 2 I/O I/O CPU 4 open/close/read/write open, read, write open/close read/write /dev
Express5800/R110a-1Hユーザーズガイド
4 Phoenix BIOS 4.0 Release 6.0.XXXX : CPU=Xeon Processor XXX MHz 0640K System RAM Passed 0127M Extended RAM Passed WARNING 0B60: DIMM group #1 has been disabled. : Press to resume, to
Quartus II ハンドブック Volume 5、セクションIV. マルチプロセッサの調整
IV. SOPC Builder Nios II 9 Avalon Mutex 10 Avalon Mailbox 9 10 / 9 v5.1.0 2005 5 v5.0.0 Nios II 2004 12 v1.0 10 v5.1.0 2005 5 v5.0.0 Altera Corporation IV 1 Quartus II Volume 5 IV 2 Altera Corporation
I 2 tutimura/ I 2 p.1/??
I 2 tutimura@mist.i.u-tokyo.ac.jp http://www.misojiro.t.u-tokyo.ac.jp/ tutimura/ 2002 4 25 I 2 p.1/?? / / Makefile I 2 p.2/?? Makefile make GNU make I 2 p.3/?? Makefile L A T E X I 2 p.4/?? core (1) gcc,
untitled
Corporate Development Division Semiconductor Company Matsushita Electric Industrial Co.,Ltd. http://www.panasonic.co.jp/semicon/ DebugFactory Builder for MN101C PanaX IDE IBM PC/AT CPU Intel Pentium 450MHz
64bit SSE2 SSE2 FPU Visual C++ 64bit Inline Assembler 4 FPU SSE2 4.1 FPU Control Word FPU 16bit R R R IC RC(2) PC(2) R R PM UM OM ZM DM IM R: reserved
(Version: 2013/7/10) Intel CPU (kashi@waseda.jp) 1 Intel CPU( AMD CPU) 64bit SIMD Inline Assemler Windows Visual C++ Linux gcc 2 FPU SSE2 Intel CPU double 8087 FPU (floating point number processing unit)
ACE Associated Computer Experts bv
CoSy Application CoSy Marcel Beemster/Yoichi Sugiyama ACE Associated Compiler Experts & Japan Novel Corporation contact: yo_sugi@jnovel.co.jp Parallel Architecture 2 VLIW SIMD MIMD 3 MIMD HW DSP VLIW/ILP
NL-22／NL-32取扱説明書_操作編
MIC / Preamp ATT NL-32 A C ATT AMP 1 AMP 2 AMP 3 FLAT FLAT CAL.SIG. OVER LOAD DET. AMP 4 AMP 5 A/D D/A CONV. AMP 6 AMP 7 A/D CONV. Vref. AMP 8 AMP 10 DC OUT AMP 9 FILTER OUT AC DC OUT AC OUT KEY SW Start
Design at a higher level
Meropa FAST 97 98 10 HLS, Mapping, Timing, HDL, GUI, Chip design Cadence, Synopsys, Sente, Triquest Ericsson, LSI Logic 1980 RTL RTL gates Applicability of design methodologies given constant size of
PBASIC 2.5 PBASIC 2.5 $PBASIC directive PIN type New DEBUG control characters DEBUGIN Line continuation for comma-delimited lists IF THEN ELSE * SELEC
PBASIC 2.5 PBASIC 2.5 BASIC Stamp Editor / Development System Version 2.0 Beta Release 2 2.0 PBASIC BASIC StampR PBASIC PBASIC PBASIC 2.5 Parallax, Inc. PBASIC 2.5 PBASIC 2.5 support@microbot-ed.com 1
Verilog HDL による回路設計記述
Verilog HDL 3 2019 4 1 / 24 ( ) (RTL) (HDL) RTL HDL アルゴリズム 動作合成 論理合成 論理回路 配置 配線 ハードウェア記述言語 シミュレーション レイアウト 2 / 24 HDL VHDL: IEEE Std 1076-1987 Ada IEEE Std 1164-1991 Verilog HDL: 1984 IEEE Std 1364-1995
ARM gcc Kunihiko IMAI 2009 1 11 ARM gcc 1 2 2 2 3 3 4 3 4.1................................. 3 4.2............................................ 4 4.3........................................
starc_verilog_hdl pptx
!!!!!!! ! 2.10.6.! RTL : 1! 1 2! 3.2.5.! : ! 1.7. FPGA 1 FPGA FPGA 1.5.2! 3.1.2.! 3! 3.3.1. DFT! LSI :! 2 : ! ON FPGA!!! FPGA! FPGA! !!!!! ! Verilog HDL 6 9 4! Xilinx ISE!!! RTL! CPU !! 20!! C! VHDL! Xilinx
エクセルソフト株式会社 WinDriver PCI 5! WinDriver 1. DriverWizard 2. DriverWizard WinDriver 1. Windows 98/Me NT/2000/XP Windows CE/CE.NET Windows Server 2003 Lin
5! WinDriver 1. DriverWizard 2. DriverWizard WinDriver 1. Windows 98/Me NT/2000/XP Windows CE/CE.NET Windows Server 2003 Linux Solaris VxWorks Web http://www.xlsoft.com/jp/products/windriver/ 2. WinDriver
[user@linux tmp]$ tar xzvf utvpn-src-unix-v100-7092-beta-2010.06.25.tar.gz [user@linux tmp]$ cd utvpn-unix-v100-7092-beta [user@linux utvpn-unix-v100-7092-beta]$ ls License-ja.txt configure makefiles src
25 II :30 16:00 (1),. Do not open this problem booklet until the start of the examination is announced. (2) 3.. Answer the following 3 proble
25 II 25 2 6 13:30 16:00 (1),. Do not open this problem boolet until the start of the examination is announced. (2) 3.. Answer the following 3 problems. Use the designated answer sheet for each problem.
Avalon Memory-Mappedブリッジ
11. Avalon emory-apped QII54020-8.0.0 Avalon emory-apped Avalon- OPC Builder Avalon- OPC Builder Avalon- OPC Builder Avalon-11 9 Avalon- Avalon- 11 12 Avalon- 11 19 OPC Builder Avalon emory-apped Design
FPGAメモリおよび定数のインシステム・アップデート
QII53012-7.2.0 15. FPGA FPGA Quartus II Joint Test Action Group JTAG FPGA FPGA FPGA Quartus II In-System Memory Content Editor FPGA 15 2 15 3 15 3 15 4 In-System Memory Content Editor Quartus II In-System
mbed_library_study_meeting_v1.0.key
mbed _mbed 2014 11 7 https://atnd.org/events/57766 version 1.0, 07-Nov.-2014 Tedd OKANO mbed - - 4.0 (^^; 1 mbed TEDD OKANO https://twitter.com/tedd_okano 10 I 2 C http://developer.mbed.org/users/okano/
For_Beginners_CAPL.indd
CAPL Vector Japan Co., Ltd. 目次 1 CAPL 03 2 CAPL 03 3 CAPL 03 4 CAPL 04 4.1 CAPL 4.2 CAPL 4.3 07 5 CAPL 08 5.1 CANoe 5.2 CANalyzer 6 CAPL 10 7 CAPL 11 7.1 CAPL 7.2 CAPL 7.3 CAPL 7.4 CAPL 16 7.5 18 8 CAPL
1, Verilog-HDL, Verilog-HDL Verilog-HDL,, FPGA,, HDL, 11, 1 (a) (b) (c) FPGA (d) 2 10,, Verilog-HDL, FPGA, 12,,,, html % netscape file://home/users11/
1 Kazutoshi Kobayashi kobayasi@ieeeorg 2002 12 10-11 1, Verilog-HDL, Verilog-HDL Verilog-HDL,, FPGA,, HDL, 11, 1 (a) (b) (c) FPGA (d) 2 10,, Verilog-HDL, FPGA, 12,,,, html % netscape file://home/users11/kobayasi/kobayasi/refresh/indexhtml,,
PowerPoint プレゼンテーション
SATA Host/Device IP Core HDD や SSD などのストレージを使用した システム開発に最適な FPGA 向けIntelliProp 社製 SATA IP Core IntelliProp 社製 SATA Host / Device IP Coreは SATA Revision 3.0 Specificationに準拠しており 1.5Gbps 3.0Gbps 6.0Gbpsに対応しています
JIIAセミナー
Digital Interface IIDC URL teli.co.jp/ E-Mail http://www.toshiba-teli.co.jp teli.co.jp/ s-itokawa@toshiba-teli.co.jpteli.co.jp EIA,NTSC EIA,NTSC 4-5 JIIA JIIA - / Digital Interface Digital Interface IEEE1394
COINS 5 2.1
COINS (0501699) 20 21 2 5 1 3 1.1....................................... 3 1.2..................................... 4 1.3....................................... 4 2 COINS 5 2.1 COINS..................................
Java updated
Java 2003.07.14 updated 3 1 Java 5 1.1 Java................................. 5 1.2 Java..................................... 5 1.3 Java................................ 6 1.3.1 Java.......................
新版明解Ｃ言語 実践編
2 List - "max.h" a, b max List - max "max.h" #define max(a, b) ((a) > (b)? (a) : (b)) max List -2 List -2 max #include "max.h" int x, y; printf("x"); printf("y"); scanf("%d", &x); scanf("%d", &y); printf("max(x,
R1EV5801MBシリーズ データシート
1M EEPROM (128-kword 8-bit) Ready/Busy and function R10DS0209JJ0100 Rev.1.00 131072 8 EEPROM ROM MONOS CMOS 128 2.7V 5.5V 150ns (max) @ Vcc=4.5V 5.5V 250ns(max) @ Vcc=2.7V 5.5V 20mW/MHz (typ) 110µW (max)
r07.dvi
19 7 ( ) 2019.4.20 1 1.1 (data structure ( (dynamic data structure 1 malloc C free C (garbage collection GC C GC(conservative GC 2 1.2 data next p 3 5 7 9 p 3 5 7 9 p 3 5 7 9 1 1: (single linked list 1
program.dvi
2001.06.19 1 programming semi ver.1.0 2001.06.19 1 GA SA 2 A 2.1 valuename = value value name = valuename # ; Fig. 1 #-----GA parameter popsize = 200 mutation rate = 0.01 crossover rate = 1.0 generation
3 PAD p.2/88
3 PAD 20050023 faculty@soi.wide.ad.jp Δ N205 2005 3 PAD p.1/88 http://www.soi.wide.ad.jp/ 3 PAD p.2/88 1: 2: PAD (Problem Analysis Diagram) 3: PAD 3 PAD p.3/88 TIPS? 3 PAD p.4/88 Cricket 1 (+ ) 1 (+ )
ohp07.dvi
19 7 ( ) 2019.4.20 1 (data structure) ( ) (dynamic data structure) 1 malloc C free 1 (static data structure) 2 (2) C (garbage collection GC) C GC(conservative GC) 2 2 conservative GC 3 data next p 3 5
Introduction Purpose This training course demonstrates the use of the High-performance Embedded Workshop (HEW), a key tool for developing software for
Introduction Purpose This training course demonstrates the use of the High-performance Embedded Workshop (HEW), a key tool for developing software for embedded systems that use microcontrollers (MCUs)
Express5800/320Fa-L/320Fa-LR
7 7 Phoenix BIOS 4.0 Release 6.0.XXXX : CPU=Pentium III Processor XXX MHz 0640K System RAM Passed 0127M Extended RAM Passed WARNING 0212: Keybord Controller Failed. : Press to resume, to setup
ohp1.dvi
2008 1 2008.10.10 1 ( 2 ) ( ) ( ) 1 2 1.5 3 2 ( ) 50:50 Ruby ( ) Ruby http://www.ruby-lang.org/ja/ Windows Windows 3 Web Web http://lecture.ecc.u-tokyo.ac.jp/~kuno/is08/ / ( / ) / @@@ ( 3 ) @@@ :!! ( )
1 osana@eee.u-ryukyu.ac.jp : FPGA : HDL, Xilinx Vivado + Digilent Nexys4 (Artix-7 100T) LSI / PC clock accurate / Artix-7 XC7A100T Kintex-7 XC7K325T : CAD Hands-on: HDL (Verilog) CAD (Vivado HLx) : 28y4
Microsoft PowerPoint - 01_Vengineer.ppt
Software Driven Verification テストプログラムは C 言語で! SystemVerilog DPI-C を使えば こんなに便利に! 2011 年 9 月 30 日 コントローラ開発本部コントローラプラットフォーム第五開発部 宮下晴信 この資料で使用するシステム名 製品名等は一般にメーカーや 団体の登録商標などになっているものもあります なお この資料の中では トレードマーク
N Express5800/R320a-E4 N Express5800/R320a-M4 ユーザーズガイド
7 7 Phoenix BIOS 4.0 Release 6.0.XXXX : CPU=Pentium III Processor XXX MHz 0640K System RAM Passed 0127M Extended RAM Passed WARNING 0212: Keybord Controller Failed. : Press to resume, to setup
Express5800/R320a-E4, Express5800/R320b-M4ユーザーズガイド
7 7 Phoenix BIOS 4.0 Release 6.0.XXXX : CPU=Pentium III Processor XXX MHz 0640K System RAM Passed 0127M Extended RAM Passed WARNING 0212: Keybord Controller Failed. : Press to resume, to setup
/ , ,908 4,196 2, ,842 38, / / 2 33 /
MathWorks Automotive Conference 2014 ( ) ECU 0.1. 1 /30 1949 12 16 1,874 4 959 2 4,908 4,196 2,993 139,842 38,581 62 26 35 56 / 6 185 13 4 3 11 / 2 33 / 2014 3 31 0.1. 2 /30 ETC 0.2. 3 /30 1. 1. 2. 2.
Cyclone IIIデバイスのI/O機能
7. Cyclone III I/O CIII51003-1.0 2 Cyclone III I/O 1 I/O 1 I/O Cyclone III I/O FPGA I/O I/O On-Chip Termination OCT Quartus II I/O Cyclone III I/O Cyclone III LAB I/O IOE I/O I/O IOE I/O 5 Cyclone III
r08.dvi
19 8 ( ) 019.4.0 1 1.1 (linked list) ( ) next ( 1) (head) (tail) ( ) top head tail head data next 1: NULL nil ( ) NULL ( NULL ) ( 1 ) (double linked list ) ( ) 1 next 1 prev 1 head cur tail head cur prev