動的適応型ハードウェアの提案
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- みりあ ちづ
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1
2 LSI A B C D CPU for i=0; i<k; i++ X[i]=X[i+j]... CPU
3 PLD 10M 1M 100K 10K PLA EEPROM SPLD FPGA CPLD SRAM FPGA /
4 Reconfigurable Systems 1990 The 1st FPL The 1st Japanese FPGA/PLD Conf. The 1st FCCM SPLASH SPLASH-2 RM-I RM-II PRISM-I PRISM-II MPLD WASMII RM-III Cache Logic YARDS RM-IV DISC RM-V DISC-II HOSMII ATTRACTOR PipeRench FIPSOC RASH CHIMERA DRL PCA Chameleon ACM DRP DAP/DNA PCA2 DAP/DNA2
5 FPGA CPUFPGA SoC FPGA
6 SoPDSystem on Programmable Device) CPU/Reconfigurable System OS FPGA FCCM
7 FPGA/CPLD SoC CPUFPGA/PLD DRP
8 I/O CPU Memory Application Specific Hardware SoC (System-on-a-Chip) CPU,Memory,I/O, LSI Cellular Phones, Network Controllers, Mobile Terminals Problem! (JPEG2000, AES,Turbo code..)!!
9 +? I/O CPU Application Common Specific FPGA Hardware FPGA Xilinx Virtex II Pro PowerPC Altera Excalibur (ARM) Memory
10 CPU+ I/O CPU Application Dynamic Reconfigurable Specific Hardware Processor Course Grain Structure Memory C-level programming
11 C-level DRP
12
13 Chameleon CS2112DPU OPOperations in C or Verilog bitbit SIMD arrays and pipelines are formed with multiple DPUs. Instruction Routing MUX Routing MUX Barrel Shifter Register Mask Register Mask OP Register Register
14 DRP-1
15
16 On-Chip Memory 10 s micro-seconds PACT Xpp Elixent s DFA On-Chip Memory
17 RGB to YCbCr Downsampling DCT Quantization VLC CPU JPEG CPU CPU
18 Input data Output data Configuration RAM ROM MPLD(1990) MPLD(1990) WASMII RAM(1992) (1992)Xilinx(1997) NECDRP(2002) DRP(2002)Partial Context switch, runtime reconfiguration Logic cells Multiplexer 1 2 n Context SRAM slots
19 Task N Task N+1
20 Task N+2 Task N+1
21 1/ /
22
23 FPGA NTT PCA-2 Elixent DFA PACT Xpp 1 NEC DRL NEC DRP PipeRench IPFlex DAP/DNA 4-5bit 8bit 16bit 32bit
24 3C-level C(BDL, Dataflow C, Stream C ASIC Verilog HDLVHDLC-level
25 / DRP
26 90 PACTxpp ElixentDFA1000 DSP NTTPCA/PCA-2
27 Xpp (PACT Informations technologie) I/O I/O PAC CM PAC CM I/O I/O I/O I/O CM PAC SCM CM PAC I/O I/O PAC: Processing Array Cluster) CM: Configuration Manager SCM: Supervising CM PAE Configuration controller Xpp64 (8x8 Configuation100 24
28 ElixentDFA1000 bit ALU Register RAM based switch box ALU R ALU R R R R R ALU R ALU R R R R R ALU R ALU R R R R R ALU R ALU R R R R R
29 PCA (Plastic Cell Architecture) NTT BP PP
30 Plastic Part LUT LUT BP LUT basic cell PP LUT 1LUT Buit-in-part Hw fork
31 Chameleon IPFlexDAP/DNA, DAP/DNA-2 NEC DRP QuicksilverACM MorphTechrDSP PicoChipPC101
32 Chameleon CS bit PCI Bus PCI Cont. RISC Core 64-bit Memory Bus Memory Controller 128-bit RoadRunner Bus Configuration Subsystem DMA Subsystem Reconfigurable Processing Fabric 160-pin Programmable I/O
33 Reconfigurable 8 instructions Processing stored in Fabric the CTL in Chameleon LM DPU are executed in the DPU. The CTL can select the next instruction in the same cycle. Configuration CTL can be LMchanged DPU by loading a bit stream. CTL Tile 0 Tile 0 Slice 0 Slice DPU(Data Path Unit)s consists 4 Slices3Tiles each 1Tile: 9DPU32bit ALU X 7 16bit + 16bit multiplier X 2
34 IPflexDAP/DNA-2 DDR SDR IF (64bit 166MHz) PCI IF (32bit 66MHz) DAP (RISC) DMA Controller Interrupt Controller Timer SROM IF GPIO UART Serial IF BSU DNA load buffer DNA store buffer DNA Matrix DNA direct I/O (Async. In) DNA direct I/O (Async. out) 368 ALU,
35 DNA SMA RAM FF FF FF FF Shift/Mask Shift/Mask Shift/Mask Shift/Mask FF FF FF FF ALU ALU ALU FF FF
36 PipeRench CMU) Global buses PE PE PE PE Pass registers Interconnection PE PE PE PE stripe Interconnection
37 Pipelined Reconfiguration Cycle: Stage 1 Stage 2 Stage 3 Virtual pipeline Stage 4 Stage 5 Cycle: Stage 1 Stage 2 Stage Physical pipeline
38 PEPC PE PE PE DSP QuicksilverACM MorphTechrDSP PicoChipPC101
39 ACM Quicksilver) Matrix Interconnect Network Adaptive Node Programmable Node Domain Node Level1 Cluster Level2 Cluster Level3 Cluster
40 Adaptive Node Domain Node Filter, Bit Programmable Scalar Node RISC CPU (ARC 1 31 Silver-C
41 RGB to YCbCr Downsampling DCT Quantization VLC AXN DBN PSN
42 RGB to YCbCr Downsampling DCT Quantization VLC AXN DAN DBN PSN
43 RGB to YCbCr Downsampling DCT Quantization VLC AXN DBN PSN AXN AXN
44 Granularity 32bit 16bit FPGA DAP/DNA CS2112 Parallelism 8 16 DRL DRP PipeRench DSP PC101 Traditional Processors ACM Chip-Multiprocessor Common Processor 8bit 10 4bit Many Time Multiplexing
45 DRP
46 NEC DRP (Dynamically Reconfigurable Processor) 16 5 PE
47 DRP-1 Tile Vmem Hmem
48 DRP Tile HMEM HMEM HMEM HMEM VMEM VMEM VMEM VMEM VMEM ctrl VMEM ctrl VMEM VMEM VMEM VMEM PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE VMEM(2-port HMEM(1-port memory) PE PE PE PE PE PE PE PE State Transition Controller 8bit 256entry 8092entry PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE PE HMEM HMEM HMEM HMEM VMEM VMEM VMEM VMEM VMEM ctrl VMEM ctrl VMEM VMEM VMEM VMEM
49 BDL DRP
50 DRPVLIWFPGA DAP/DNA Granularity 32bit 16bit FPGA CS2112 Parallelism 8 16 DRL DRP PipeRench DSP PC101 ACM Chip-Multiprocessor Common Processor 8bit 10 4bit Many Time Multiplexing
51 WASMIIDRP WASMII DRP DRP Configuration Data line Execution Input Token Registers Control
52 MDCT CPU DRP Window: 18 MDCT
53 DRP-1MDCT Cosine Window I Butterfly Function Cosine Windows II N-point DCT N-point DCT Subtraction Window Function
54 DRP-1 576/2 +2 Stream IN 32(24) /2 Stream OUT 51clk X 45ns = 2295ns/ Pentium III 600MHz1,8
55 Stream Data in Stream Data out
56 BDL( Behavior Description Language) gcc Musketeer
57 RTL
58 Van del Pol/ Neural NetworkFPGA/PLD Conf Wavelet(CPSY MDCTCoolChipsVI ViterbiReconf I RC6Reconf III Reconf III FPL MINReconf III Musketeer FFTFPGA/PLD Conf FCCM MDCT CPSY: Reconf:
59 FFT DRP DRP MIPS64 TI DSP MHz 33MHz 500MHz 225MHz FFT/
60 C DWT 14 61MHz Pentium III(600M) Pentium III(600M)1.8 Viterbi 12 33MHz Pentium IV 2.4G5 RC MHz MIPS64(500M)6 TMS320C6713(225M) Pentium IV(2.5G)3 TMS32C6713(225M)17
61 DRP Open Problem
62 Chameleon Configurable Processor DSP FPGA/CPLD System On Chip
63 Open Problems Configuration Configuration Processing Element 8-32bit Xilinx DRP ACM,IPFlex
64 Reconfigurable Architecture Big Problem ISA (Instruction Set Architecture) Reconfigurable Architecture
65 SARAStream processing architecture with Reconfigurable processor array) Network-On-Chip: Black-bus DRPSARA MP3WaveletJPEG2000Viterbi coderalpha blender
66 SARA (Stream processing Architecture with Reconfigurable processor Array) DRP I/O data CPU RAM Stream I/O controller Tile Tile Tile Tile Interconnection Network Tile Tile Tile Tile Context Shared Memory Local STC PE Global STC Context loading controller Configuration data
67 TileBlack-bus Router (0,0) Send( D0, 0 ) Send( D1, 1 ) Receive( 0, task1 ) Task 1 (1,0) (2,0) (3,0) (D0,ID=3) (D0,ID=0) Task 2 0 =(013) (D1,ID=1) (0,0) (1,0) (D0,ID=1) (2,0) (D1,ID=2) (0,1) (1,1) (D1,ID=1) Receive( 1, task1 ) (2,1) (3,1) (D1,ID=0) Task 3 1 =(1210) (0,1) (1,1) (2,1) ID ID ID ID
68 VHw (NEC2004 VH VH
69 Hw A A A1 A2 A3 A4 A6 A5
70 Fixed Region A1 A A A1 A2 A3 A4 A6 A5
71 Fixed Region A A5 A A1 A2 A3 A4 A6 A5
72 Fixed Region A1 A A7 A A4 A A2 A7 A3 A A6 A5
73 / OSCPU University Program DRP, DAP/DNA-2
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E-mail: yamasaki@{ics.keio.ac.jp, etl.go.jp} http://www.ny.ics.keio.ac.jp etc. CPU) I/O I/O or Home Automation, Factory Automation, (SPARC) (SDRAM I/F, DMAC, PCI, USB, Timers/Counters, SIO, PIO, )
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13 Verilog HDL 16 CPU CPU IP 16 1023 2 reg[ msb: lsb] [ ]; reg [15:0] MEM [0:1023]; //16 1024 16 1 16 2 FF 1 address 8 64 `resetall `timescale 1ns/10ps module mem8(address, readdata,writedata, write, read);
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352 Vol. 19 No. 3, pp.352 361, 2001 1 2 Responsive Processor for Parallel/Distributed Real Time Control Nobuyuki Yamasaki 1 and Toshihiro Matsui 2 In this paper, we propose and design Responsive Processor
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