!!!!!!!
! 2.10.6.! RTL : 1! 1 2! 3.2.5.! :
! 1.7. FPGA 1 FPGA FPGA 1.5.2! 3.1.2.! 3! 3.3.1. DFT! LSI :! 2 :
! ON FPGA!!! FPGA! FPGA!
!!!!!
! Verilog HDL 6 9 4! Xilinx ISE!!! RTL! CPU
!! 20!! C! VHDL! Xilinx FPGA!
http://www.sessame.jp/ MISRA-C MISRA-C MISRA-C MISRA-C ISBN:4542503348 3,570 2004 5 13 http://www.sessame.jp/ workinggroup/workinggroup3/misra-c_guigebook.htm MISRA-C MISRA-C MISRA-C SESSAME
! MISRA-C!!!!! RTL! HDL,!!!
!!!!!!
(Design automation)/ (Behavioural languages) IEEE IEC VHDL, Verilog-HDL RTL (STARC:Semiconductor Technology Academic Research Center) Xilinx Altera 1 HDL
! (Design automation)/hdl : IEEE! VHDL:VHSIC Hardware Description Language! VHSIC: Very High Speed Integrated Circuits! Verilog-HDL! (Behavioural languages):iec! IEEE
IEC/IEEE 61691-1-1, Part 1: VHDL language reference manual IEC/IEEE 61691-2, Part 2: VHDL multilogic system for model interoperability IEC/IEEE 61691-3-2, Part 3-2: Mathematical operation in VHDL IEC/IEEE 61691-3-3, Part 3-3: Synthesis in VHDL) IEC/IEEE 61691-4, Part 4: Verilog hardware description language IEC/IEEE 61691-6, Part 6: VHDL Analog and Mixed-Signal Extensions IEC/IEEE 61961-7, Part7: System C Language Reference Manual IEC 62530/IEEE Std 1800-2005: Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language
! http://www.dasc.org/new_working-groups.html! VHDL Working Groups! P1076 Standard VHDL Language Reference Manual (VASG)! P1076.1 Standard VHDL Analog and Mixed-Signal Extensions (VHDL-AMS)! P1076.1.1 Standard VHDL Analog and Mixed-Signal Extensions - Packages for Multiple Energy Domain Support (StdPkgs)! P1076.4 Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification (VITAL)! P1800 SystemVerilog: Unified Hardware Design, Specification and Verification Language! P1850 Standard for PSL: Property Specification Language
(cont.)! P1481 Standard for Integrated Circuit (IC) Open Library Architecture (OLA)! P1647 Standard for the Functional Verification Language 'e' (ewg)! P1666 Standard System C Language Reference Manual (system c)! P1685 SPIRIT XML Standard for IP Description! P1699 Rosetta System Level Design Language Standard! P1735 Recommended Practice for Encryption and [Use Rights] Management of Electronic Design Intellectual Property (IP)! P1778 ESTEREL v7 Language Standardization! P1801 Standard for the Design & Verification of Low Power ICs
! P1076.2 IEEE Standard VHDL Mathematical Packages (math)! P1076.3 Standard VHDL Synthesis Packages (vhdlsynth)! P1164 Standard Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164) (vhdl-std-logic)! P1364.1 Standard for Verilog Register Transfer Level Synthesis (VLOG-Synth)! P1497 Standard for Standard Delay Format (SDF) for the Electronic Design Process! P1499 Standard Interface for Hardware Description Models of Electronic Components! P1577 Object Oriented VHDL (oovhdl)! P1603 Standard for an Advanced Library Format (ALF) Describing Integrated Circuit (IC) Technology, Cells, and Blocks! P1604 Library IEEE! P1076.6 Standard for VHDL Register Transfer Level (RTL) Synthesis
! Chairman : Mr Osamu Karatsu (JP)! Liaisons : Internal IEC Liaison : SC 3D, SC 23J, SC 65E, TC 91! Liaison ISO : ISO/TC 44/SC 12, ISO/TC 184! Working Group :! WG 1 - Electronical data harmonization (Approaches, methodologies and technologies)! WG 2 - Component, circuit and system description languages! WG 3 - Product Data Exchange (PDX) characteristics and methodology! WG 5 - Test, validation, conformance and qualification technologies! WG 6 - Library of Reusable Parts for Electrotechnical Products! WG 7 - Testing of Electrotechnical Products! Joint Working Group : JWG 11 - Product description standard for printed board, printed board assembly, and testing in XML schema
VHDL Verilog-HDL 600 VHDL Verilog-HLD 2 (pdf 2 )
!!!!!!!
! <1>,<2>,<3>,<4>! (A.x), (B.x), (C.x), (D.x)! Verilog 2.0! RTL!!
(A) A.1 1.1 <1> A.2 <2> 1.2 (A.2.1) 1.3 (A2.2) 1.4 (A.2.3) 1.5 (A.2.4) A.3 <4> 1.6 (A.3.1) 1.7 FPGA(A.3.2)<Verilog-HDL ver.2>
(B) B.1 always <2> 2.1 (B.1.1) 2.2 always (B.1.2) 2.3 FF (B.1.3) 2.4 (B.1.4) 2.5 (B.1.5) 2.6 always (B.1.6) B.2 <2> 2.7 if (B.2.1) 2.8 case (B.2.2) 2.9 for (B.2.3) B.3 RTL 2.10 (B.3.1) <2> 2.11 (B.3.2) <3>
(C) C.1 <3> 3.1 (C.1.1) 3.2 (C.1.2) 3.3 (DFT)(C.2) <4> 3.4 (C.3) <3> 3.5, (C.4) <1>
(D) D.1 (test bench) 4.1 (D.1.1) <2> 4.2 (Task description)(d.1.2) <3> 4.3 (Verification process )(D.2) <3> 4.4 (simulation)(d.3) <4> 4.5 (static) (timing) (D.4) <3>
! 1.1.1.! 1.1.2.! 1.1.3.! 1.1.4. include define (VHDL )! 1.1.5.
! < >.v (Verilog) [ 2]! _ [ ]! Verilog HDL(IEEE1364), SystemVerilog(IEEE1800), VHDL(IEEE1076.X) [ ]! VDD, VSS, VCC, GND, VREF [ ]! / (Abc,abc ) [ ] OS! _ [ 1]! ( _X, _N ) [ 2]< _X _N >! < >_< > (Verilog) [ 3]! 16 / [ 1]! ASIC [ ]
! 2 32 [ ] 1 1! 16 2! 128 3! (TOP) ( ) [ 3]! [ 3]! < > + _ [ 3]! [ ]! [ 2]! 2
! [ ]! [ ]! define 2 40 (Verilog) [ ] 1 1! 24 2
! include RTL.h,.vh,.inc.h,.inc,.ht,.tsk (Verilog HDL only) [ 2]! (Verilog) [ 3]! (Verilog) [ 3]! define (Verilog HDL only) [ 1]! 1 [ ]! [ 1]!! [ 3]! < > b, h, d, o (Verilog HDL only) [ 1]! 32 (Verilog HDL only)! [ ]
! [ 3]! CLK CK RST_X RESET_X EN [ 3]! [ ]! [ ]
! 1 FPGA [ 1]! FPGA ASIC CORE [ ]! FPGA, ASIC `ifdef [ ]
! 3.5.1.! 3.5.2.! 3.5.3.! 3.5.4.! 3.5.5.! 3.5.6.! (3.5.7. CVS )! (3.5.8. CVS )! (3.5.9. CVS )! (3.5.10. CVS )! 3.5.11.
! RTL Sim [ ]! RTL [ 1]! [ 2]! [ 1]
! 1 master [ 1]! RTL < >.v (Verilog) [ 1]! _tb.v, _test.v,.vt (Verilog) [ 3]! < >.v.vnet (Verilog) [ 3]! include RTL ".h",".vh",".inc" ".h",".inc",".ht",".tsk" (Verilog HDL only) [ 2]! Unix.run [ 3]! (Verilog HDL).v_scr [ 3]! lint.l_scr [ 3]!.scr [ 3]! log.log [ 3]! lint log.l_log [ 3]!.rep.tim.ara [ 3]! SDF.sdf [ 1]! EDIF.edif.edf [ 1]!.db [ 1]
! [ 1]! [ 1]! [ 1]! CVS [ 3] < : RCS Subversion CVS >
! [ 1]! CVS [ ]! < : RCS Subversion CVS >
! [ 2]! [ 2]! < >
[ 2] [ 2] 1 [ 2] [ 2] EDA [ ] EUC [ 1] // [ 3]
!!!!! //! /* */ /* /* MISRA-C! /* */
!!
10 SWEST2008 10 (KWIC:key word in context)
RTL1.2 46
RTL1.3