Verilog HDL 3 2019 4 1 / 24
( ) (RTL) (HDL) RTL HDL アルゴリズム 動作合成 論理合成 論理回路 配置 配線 ハードウェア記述言語 シミュレーション レイアウト 2 / 24
HDL VHDL: IEEE Std 1076-1987 Ada IEEE Std 1164-1991 Verilog HDL: 1984 IEEE Std 1364-1995 C SFL (NTT) UDL/I (JEITA) SpecC, SystemC, SystemVerilog: C, C++ HDL 3 / 24
Verilog HDL [1984] IEEE [1995] HDL [1990 ] IEEE [2001] ( Verilog-2001 ) C { } begin end : 4 / 24
: 4 adder4.v module adder4 ( input [3:0] a, b, input cin, output [3:0] sum, output cout ); a[3:0] b[3:0] cin {cout, sum} = a + b + cin sum[3:0] cout assign { cout, sum } = a + b + cin ; endmodule module 5 / 24
1 0, 1, x, z 4 x: ( ) z: signed ( ) (b,o,h,d) 4 b1010 16 h0a3f 10 32 x, z _ 8 bxx10 111x ( ) wire reg FF parameter integer 6 / 24
wire: wire data 1 / [n:m] ( ) wire [3:0] data 4 ( ) data 4 data[3:1] 3 reg: ( ) reg [3:0] data [0:255] 4 256 ( ) data[5] 4 data[5][3:1] 3 wire reg reg input, output, inout wire ( ) output reg 7 / 24
C (+,-,*,/,%) (&,,^,~) (?:) / (&&,==,!=,>=, ) Verilog HDL {a, b} 1 &a, a ( ) wire assign function always 8 / 24
always always ( ) @ ( ) begin end ( ) initial 1 ( ) #n 9 / 24
function function [ ] ; endfunction assign always function decode2 4 function [3:0] decode2_4 ; input [1:0] a; begin case (a) 0: decode2_4 = 4 b0001 ; 1: decode2_4 = 4 b0010 ; 2: decode2_4 = 4 b0100 ; default : decode2_4 = 4 b1000 ; endcase end endfunction assign x = decode2_4 ( x_bin ); 10 / 24
function always for, while, repeat ( ) if if ( ) begin end else begin end case case (default ) ( if... else if... )? (= z ) don t care casez ( x don t care casex ) case ( ) 1: // 2: default : endcase 11 / 24
submodule instantiation wire [7:0] op1, op2, sum ; wire c0, c4, c8; adder4 a0 (.a( op1 [3:0]),.b( op2 [3:0]),. cin (c0),. sum ( sum [3:0]),. cout (c4)); adder4 a1 (.a( op1 [7:4]),.b( op2 [7:4]),. cin (c0),. sum ( sum [7:4]),. cout (c8)); wire reg 12 / 24
module structure module ( ); wire/reg ; assign always endmodule assign always wire reg 13 / 24
: 4 count4.v module count4 ( input reset, clock, output reg [3:0] data ); reset clock always @( posedge clock or negedge reset ) begin if ( reset == 1 b0) begin data <= 4 b0000 ; end else begin data <= data + 1; end end endmodule reg always data[3:0] 14 / 24
always 0 @() ( ) always @(posedge clock) ( reset==0 ) always @(posedge clock, negedge reset) always ( @* always comb ) 15 / 24
/ (=) wire (<=) reg Blocking A = B; B = A; Nonblocking // A <= B; B <= A; // A B 16 / 24
always (function : ) always @( posedge clock ) begin s = x + y + c; end always @( x or y) begin s = x + y + c; end always @( x or y or c) begin s = x + y + c; end always @* begin if ( c ==0) s = x + y; end 17 / 24
HDL ( ) RTL : HDL : HDL テストベンチ テスト対象 テストパタンクロック生成入力波形生成出力を期待値と比較 18 / 24
timescale include #n initial 0 1 $monitor test count4.v t i m e s c a l e 1 ns / 1 ns i n c l u d e count4. v module t ; r e g r e s e t, c l o c k ; w i r e [ 3 : 0 ] data ; count4 c1 ( r e s e t, c l o c k, data ) ; a l w a y s b e g i n #10 c l o c k = c l o c k ; end i n i t i a l b e g i n $monitor ( %d %h %h %h, $time, r e s e t, c l o c k, data ) ; r e s e t = 1 ; c l o c k = 0 ; #35 r e s e t = 0 ; #5 r e s e t = 1 ; #200 r e s e t = 0 ; #140 r e s e t = 1 ; #1000 $ f i n i s h ; end endmodule 19 / 24
FPGA FPGA ( ) reg reg [3:0] count = 4 b0001; initial reg [3:0] count ; initial begin count <= 4 b0001 ; 20 / 24
1/3 RTL wire/reg wire/reg (assign always ) 21 / 24
2/3 if else case default 0 signed unsigned unsigned 10 32-bit unsigned signed unsigned 22 / 24
3/3 RTL function 0/1 23 / 24
( ) <ktakagi@i.kyoto-u.ac.jp> 24 / 24