QII Quartus II TimeQuest Quartus II TimeQuest ASIC Quartus II TimeQuest GUI Quartus II TimeQuest GUI Synopsys Design Constraints SDC Qua

Transcription

1 QII Quartus II TimeQuest Quartus II TimeQuest ASIC Quartus II TimeQuest GUI Quartus II TimeQuest GUI Synopsys Design Constraints SDC Quartus II Quartus II TimeQuest Report Console Quartus II TimeQuest Quartus II TimeQuest FPGA HardCopy ASIC Quartus II TimeQuest 7 3 Quartus II TimeQuest Quartus II TimeQuest SDC Altera Corporation 7 1

2 Quartus II Volume I/O TimeQuest GUI TimeQuest SOPC Builder Quartus II Volume 4 SOPC Builder Quartus II TimeQuest Quartus II TimeQuest FPGA Quartus II TimeQuest Quartus II TimeQuest Quartus II v7.2 Quartus II TimeQuest Quartus II 2 Quartus II TimeQuest Quartus II TimeQuest Quartus II TimeQuest Assignments Settings Settings Category Timing Analysis Settings Use TimeQuest Timing Analyzer during compilation Quartus II TimeQuest Tools Customize Customize Toolbars Processing Close 7 2 Altera Corporation

3 Quartus II TimeQuest Quartus II TimeQuest Quartus II TimeQuest Quartus II TimeQuest 7 1 Quartus II TimeQuest 7 1. Quartus II TimeQuest Create Quartus II Project and Specify Design Files Perform Initial Compilation Specify Timing Requirements Perform Compilation Verify Timing Quartus II FPGA EDA HDL Altera Corporation 7 3

4 Quartus II Volume 3 Analysis and Synthesis SDC SDC Project Add/Remove Files in Project Files SDC FPGA TimeQuest Quartus II TimeQuest 7 27 Quartus II TimeQuest 7 4 Altera Corporation

5 Quartus II TimeQuest Quartus II TimeQuest Quartus II TimeQuest Quartus II Quartus II TimeQuest Quartus II Quartus II TimeQuest Quartus II Tools TimeQuest Timing Analyzer Quartus II TimeQuest Analysis and Synthesis Quartus II TimeQuest TimeQuest Quartus II Quartus II TimeQuest quartus_staw Tasks Open Project Altera Corporation 7 5

6 Quartus II Volume 3 Quartus II TimeQuest h --help quartus_sta -t <script file> --script=<script file> <script file> -s --shell --tcl_eval <tcl command> --do_report_timing --force_dat --lower_priority --post_map --qsf2sdc --sdc=<sdc file> --fast_model --report_script=<script> --speed=<value> --tq2hc --tq2pt Tcl <tcl command> report_timing -npaths 1 -to_clock $clock quartus_sta Quartus II.qsf Synopsys Design Constraints SDC Quartus II TimeQuest SDC HardCopy Design Center HCDC PrimeTime SDC Quartus II TimeQuest SDC PrimeTime SDC -f <argument file> -c <revision name> --rev=<revision_name> --multicorner Quartus II.qsf 7 6 Altera Corporation

7 Quartus II TimeQuest quartus_sta <options> Quartus II TimeQuest Quartus II TimeQuest Quartus II TimeQuest Quartus II TimeQuest Open Project project_open Create Timing Netlist create_timing_netlist Constrain Create Timing the Design Netlist create_clock create_timing_netlist create_generated_clock set_clock_uncertainty derive_pll_clocks set_clock_latency set_input_delay set_output_delay,... UpdateTiming Netlist update_timing_netlist Verify Static Timing Analysis Results report_clocks_transfers report_min_pulse_width report_net_timing report_sdc report_timing report_clocks report_min_pulse_width report_ucp Altera Corporation 7 7

8 Quartus II Volume 3 7 2Quartus II TimeQuest 7 2. Quartus II TimeQuest Nodes Keepers Cells Pins Nets Ports Clocks (1) LUTDSP TriMatrix IOE (2) 7 2 : (1) -from (2) Stratix LUT LE Quartus II TimeQuest 7 3 Quartus II TimeQuest data1 reg1 and_inst reg3 data2 reg2 clk 7 8 Altera Corporation

9 7 4. Quartus II TimeQuest Cells Cell data1 data2 combout Pin datain clk reg1 reg2 regout datac datad Cell and_inst combout reg3 datain data_out regout Port clk inclk0] clk~clkctrl Pin outclk Port 7 4 reg1 reg2 and_inst data1 combout reg1 regout and_inst combout data1~combout reg1 and_inst data1, clk data_out 2 Altera Corporation 7 9

10 Quartus II Volume clk Clock Path D CLRN Q Data Path D CLRN Q Asynchronous Clear Path rst Quartus II TimeQuest Quartus II TimeQuest clock-to-out µt CO Q D µt CO FPGA clock-to-out Quartus II TimeQuest 7 6 Quartus II TimeQuest µt SU µt SU FPGA 7 10 Altera Corporation

11 7 6. D Q Data Arrival D Q Clock Arrival Quartus II TimeQuest 7 7 reg1 0ns reg2 5 ns 7 7. D Q D Q clk reg1 reg2 Launch Edge at Source Register reg1 Latch Edge at Destination Register reg2 clk 0 ns 5 ns 10 ns 15 ns Altera Corporation 7 11

12 Quartus II Volume 3 Quartus II TimeQuest I/O Quartus II TimeQuest Quartus II TimeQuest Quartus II TimeQuest Quartus II TimeQuest A B 10 ns 3ns A 20 ns 19 ns B 7 8. Source Clock Setup A Setup B Destination Clock 0 ns 8 ns 16 ns 24 ns 30 ns 7 12 Altera Corporation

13 Quartus II TimeQuest Quartus II TimeQuest 1 (1) Clock Setup Slack = Data Required Time Data Arrival Time Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + µt CO + Register-to-Register Delay Data Required = Clock Arrival Time µt SU Setup Uncertainty Clock Arrival Time = Latch Edge + Clock Network Delay to Destination Register Quartus II TimeQuest 2 (2) Clock Setup Slack Time = Data Required Time Data Arrival Time Data Arrival Time = Launch Edge + Clock Network Delay + Input Maximum Delay of Pin + Pin-to-Register Delay Data Required Time = Latch Edge + Clock Network Delay to Destination Register µt SU Quartus II TimeQuest 3 (3) Clock Setup Slack Time = Data Required Time Data Arrival Time Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + µt CO + Register-to-Pin Delay Data Required Time = Latch Edge + Clock Network Delay Output Maximum Delay of Pin Altera Corporation 7 13

14 Quartus II Volume 3 Quartus II TimeQuest Quartus II TimeQuest Quartus II TimeQuest A B 2 A B A1 B1 2 A B A2 B Source Clock Hold Check A1 Setup A Hold Check A2 Hold Check B1 Setup B Hold Check B2 Destination Clock 0 ns 8 ns 16 ns 24 ns 30 ns Quartus II TimeQuest 7 9 A Altera Corporation

15 Quartus II TimeQuest 4 (4) Clock Hold Slack = Data Arrival Time Data Required Time Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + µt CO + Register-to-Register Delay Data Required Time = Clock Arrival Time + µt H + Hold Uncertainty Clock Arrival Time = Latch Edge + Clock Network Delay to Destination Register Quartus II TimeQuest 5 (5) Clock Setup Slack Time = Data Arrival Time Data Required Time Data Arrival Time = Launch Edge + Clock Network Delay + Input Minimum Delay of Pin + Pin-to-Register Delay Data Required Time = Latch Edge + Clock Network Delay to Destination Register + µt H Quartus II TimeQuest 6 (6) Clock Setup Slack Time = Data Arrival Time Data Required Time Data Arrival Time = Latch Edge + Clock Network Delay to Source Register + µt CO + Register-to-Pin Delay Data Required Time = Latch Edge + Clock Network Delay Output Minimum Delay of Pin Altera Corporation 7 15

16 Quartus II Volume 3 clear preset Quartus II TimeQuest 7 (7) Recovery Slack Time = Data Required Time Data Arrival Time Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + µt CO + Register-to-Register Delay Data Required Time = Latch Edge + Clock Network Delay to Destination Register µt SU Quartus II TimeQuest 8 (8) Recovery Slack Time = Data Required Time Data Arrival Time Data Arrival Time = Launch Edge + Clock Network Delay + Maximum Input Delay + Port-to-Register Delay Data Required Time = Latch Edge + Clock Network Delay to Destination Register Delay µt SU I/O Input Maximum Delay Quartus II TimeQuest Quartus II TimeQuest Quartus II TimeQuest Altera Corporation

17 (9) Removal Slack Time = Data Arrival Time Data Required Time Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + µt CO of Source Register + Register-to-Register Delay Data Required Time = Latch Edge + Clock Network Delay to Destination Register + µt H Quartus II TimeQuest 10 (10) Removal Slack Time = Data Arrival Time Data Required Time Data Arrival Time = Launch Edge + Clock Network Delay + Input Minimum Delay of Pin + Minimum Pin-to-Register Delay Data Required Time = Latch Edge + Clock Network Delay to Destination Register + µt H Input Minimum Delay Quartus II TimeQuest Altera Corporation 7 17

18 Quartus II Volume D Q D Q ENA D Q D Q ENA ENA 2 Cycles 7 11 src_clk 10 ns dst_clk 5ns reg reg data_in src_clk D Q D Q data_out dst_clk ns 0ns 7 18 Altera Corporation

19 7 12. setup hold set_multicycle_path 7 3 Quartus II TimeQuest 7 3. set_multicycle_path -setup -end set_multicycle_path -setup -start set_multicycle_path -hold -end set_multicycle_path -hold -start ns 10 ns new setup default setup Altera Corporation 7 19

20 Quartus II Volume 3 High Low High Low Synchronization Chain Clock 1 Domain Clock 2 Domain DATA D Q D Q D Q OUTPUT CLOCK 1 CLOCK Altera Corporation

21 Synchronization Chain Clock 1 Domain Clock 2 Domain DATA SET SET D Q D Q SET D Q OUTPUT CLR Q CLR Q CLR Q CLOCK 1 CLOCK 2 CLOCK 2 SET D Q Reg C Q CLOCK 2 clock-to-output t CO t CO t MET t MET 7 16 t MET Altera Corporation 7 21

22 Quartus II Volume DATA CLK t SU t H Q t CO t MET t MET 11 MTBF (11) ( e C 2 t MET ) MTBF = C 1 f CLOCK f DATA MTBF C1 C2 TimeQuest TimeQuest MTBF MTBF Quartus II MTBF Quartus II MTBF TimeQuest 7 70 report_metastability 7 22 Altera Corporation

23 TimeQuest Quartus II Volume 2 CCPP CCPP B D Q clk A 5.5 ns 5.0 ns 2.2 ns 2.0 ns C reg1 D Q 3.2 ns 3.0 ns 2.2 ns 2.0 ns reg2 A reg1 reg2 5.0 ns 5.5 ns CCPP CCPP 0.5 ns CCPP Altera Corporation 7 23

24 Quartus II Volume CCPP 0.7 ns CCPP 1.2 ns CCPP High Low 7 18 High Low Minimum and Maximum Rise Rise Arrival Times High Pulse Width Minimum and Maximum Fall Arrival Times Low Pulse Width CCPP ns 0.2 ns 0.3 ns 0.8 ns 0.5 ns 0.2 ns 0.9 ns 0.7 ns 7 24 Altera Corporation

25 TimeQuest CCPP 7 75 report_min_pulse_width Enable common clock path pessimism removal CCPP Settings TimeQuest settings CCPP TimeQuest Tcl enable_ccpp_removal Clock-As-Data FPGA 2 FPGA clk_in clk_out clk_in reg_data clk_in clk_out 7 19 clk_in clk_out D Q reg_data clk_in clk_out Altera Corporation 7 25

26 Quartus II Volume 3 Clock-As-Data TimeQuest PLL PLL Clock-As-Data D Q D Q Launch Clock (1/2 T) Data Arrival Time Latch Clock (T) 7 26 Altera Corporation

27 Quartus II TimeQuest Quartus II TimeQuest 7 21 TimeQuest TimeQuest Create a Timing Netlist Read Synopsys Design Constraints File Update Timing Netlist Generate Timing Reports 7 21 Tasks Create Timing Netlist Console create_timing_netlist Synopsys Design Constraints SDC SDC SDC Task Console Altera Corporation 7 27

28 Quartus II Volume 3 Tasks SDC Read SDC File Read SDC File <current revision>.sdc Console SDC Console read_sdc TimeQuest SDC 7 32 Synopsys Design Constraints SDC TimeQuest Tasks Update Timing Netlist Console update_timing_netlist Tasks 7 66 API Application Program Interface SDC & TimeQuest API Reference Manual 7 28 Altera Corporation

29 Tcl TimeQuest Quick Start Tutorial Quartus II TimeQuest API API Quartus II TimeQuest Tcl 7 4 Quartus II TimeQuest 7 4. all_clocks all_inputs all_outputs all_registers get_cells get_clocks get_nets get_pins get_ports set_multicycle_path -from -to Altera Corporation 7 29

30 Quartus II Volume Quartus II TimeQuest SDC 7 5. SDC get_fanouts <filter> get_keepers <filter> get_nodes <filter> get_partitions <filter> get_registers <filter> get_fanins <filter> derive_pll_clocks get_assignment_groups <filter> remove_clock <clock list> set_scc_mode <size> set_time_format <filter> get_nodes <filter> <filter> PLL MegaWizard Plug-In Manager PLL Assignment (Time) Groups Quartus.qsf <clock list> SCC Strongly Connected Component Quartus II TimeQuest SCC SDC SDC and TimeQuest API Reference Manual 7 1 create_clock create_generated_clock 7 1. create_clock set_multicycle_path # 60 % 10 ns create_clock -period 10 -waveform {0 6} -name clk [get_ports clk] # clk # set_multicycle_path -to [get_clocks clk] Altera Corporation

31 SDC SDC Quartus II TimeQuest SDC SDC SDC SDC Tcl SDC Quartus II SDC TimeQuest GUI write_sdc Quartus II TimeQuest Constraints Write SDC FileSDC SDC clk SDC Quartus II Quartus II TimeQuest SDC SDC SDC Quartus II TimeQuest SDC SDC Quartus II SDC Tcl set_global_assignment -name SDC_FILE <SDC file name> Quartus IIGUIProject Add/Remove Files in Project SDC Altera Corporation 7 31

32 Quartus II Volume 3 Compilation Report SDC Quartus II TimeQuest SDC SDC Quartus II TimeQuest SDC SDC SDC Quartus II TimeQuest SDC read_sdc [<SDC file name>] TimeQuest GUI SDC Quartus II TimeQuest Constraints Read SDC File Tasks Read SDC File Quartus II.qsf SDC SDC Synopsys Design Constraints Quartus II Quartus II TimeQuest SDC QSF Quartus II 7 22 SDC 7 32 Altera Corporation

33 7 22. Synopsys Design Constraints Is the SDC File Specified in the Add Files to Project Dialog Box? Yes No Does the SDC File <current revision>.sdc Exist? Yes No Manually create SDC File <current revision>.sdc Based on the Current Quartus Settings File (1) Compilation Flow 7 22 : (1) Quartus II TimeQuest Quartus II Quartus II TimeQuest SDC SDC QSF read_sdc 7 22 Quartus II TimeQuest SDC SDC API create_clock 7 2 create_clock Altera Corporation 7 33

34 Quartus II Volume create_clock create_clock -period <period value> [-name <clock name>] [-waveform <edge list>] [-add] <targets> 7 6 create_clock 7 6. create_clock -period <period value> -name <clock name> -waveform <edge list> -add <targets> -period <num>mhz (1) sysclock edge list 0ns 5ns 10 ns -waveform {0 5} 1 edge list {0 <period>/2} 50% : (1) Quartus II TimeQuest ns % 10 ns clk 0ns MHz create_clock period 10 waveform { 0 5 } clk 7 34 Altera Corporation

35 7 4 clk_sys 90 50% 10 ns MHz create_clock period 10 waveform { } clk_sys create_clock Quartus II TimeQuest Quartus II TimeQuest Quartus II TimeQuest create_generated_clock 7 5 create_generated_clock 7 5. create_generated_clock create_generated_clock [-name <clock name>] -source <master pin> [-edges <edge list>] [-edge_shift <shift list>] [-divide_by <factor>] [-multiply_by <factor>] [-duty_cycle <percent>] [-add] [-invert] [-master_clock <clock>] [-phase <phase>] [-offset <offset>] <targets> Altera Corporation 7 35

36 Quartus II Volume create_generated_clock 7 7. create_generated_clock -name <clock name> -source <master pin> -edges <edge list> -edge_shift <shift list> -divide_by <factor> -multiply_by <factor> -duty_cycle <percent> -add -invert -master_clock <clock> -phase <phase> -offset <offset> <targets> clk_x2 <master pin> -edges 1..<n> <edge list> 2 -edge_shift <edge list> -invert -edges -edge_shifts (1) -divide_by -multiply_by -divide_by 2 -edges {1 3 5} Quartus II TimeQuest -master_clock 7 7 : (1) Quartus II TimeQuest edge list Altera Corporation

37 set_clock_ latency -source ns create_clock -period 10 [get_ports clk] create_generated_clock -divide_by 1 -invert -source [get_registers clk] \ [get_registers gen clkreg] Edges clk gen clkreg Time Altera Corporation 7 37

38 Quartus II Volume edges -edge_shift create_clock -period 10 -waveform { 0 5} [get_ports clk] # divide-by-2 create_generated_clock -source [get_ports clk] -edges {1 3 5 } [get_registers \ clkdiva clkreg] # 50% divide-by-2 create_generated_clock -source [get_ports clk] -edges {1 1 5} -edge_shift { } \ [get_registers clkdivb clkreg] Edges clk clkdiva clkreg clkdivb clkreg Time multiply_by create_clock -period 10 -waveform { 0 5 } [get_ports clk] # multiply-by-2 create_generated_clock -source [get_ports clk] -multiply_by 2 [get_registers \ clkmult clkreg] clk clkmult clkreg Time Altera Corporation

39 create_clock set_input_delay set_output_delay 7 26 Quartus II TimeQuest virt_clk virt_clk ns virt_clk 50% 0ns Altera FPGA reg_a dataout datain External Device reg_b system_clk virt_clk Altera Corporation 7 39

40 Quartus II Volume # create_clock -period 5 [get_ports system_clk] # create_clock -period 10 -name virt_clk -waveform { 0 5 } # set_output_delay -clock virt_clk -max 1.5 [get_ports dataout] % ns create_clock -name virt_clk period 10 waveform { } 1 create_clock add 7 8 clk 10 ns 15 ns Quartus II TimeQuest 7 8. create_clock period 10 name clock_primary waveform { 0 5 } [get_ports clk] create_clock period 15 name clock_secondary waveform { } [get_ports clk] -add derive_clocks 7 40 Altera Corporation

41 7 9 derive_clocks 7 9. derive_clocks derive_clocks [-period <period value>] [-waveform <edge list>] 7 8 derive_clocks 7 8. derive_clocks -period <period value> -waveform <edge list> -period <num>mhz (1) edge list 0ns 5ns 10 ns edge list waveform {0 5} 1 edge list {0 period/2} 50% 7 8 : (1) ns derive_clocks PLL derive_clocks create_clock derive_clocks create_clock create_generated_clock PLL PLL PLL PLL Altera Corporation 7 41

42 Quartus II Volume 3 create_generated_clock PLL derive_pll_clocks PLL PLL derive_pll_clocks PLL 7 10 derive_pll_clocks derive_pll_clocks derive_pll_clocks [-create_base_clocks] [-use_tan_name] 7 9 derive_pll_clocks 7 9. derive_pll_clocks -use_tan_name Quartus II -create_base_clocks PLL derive_pll_clockscreate_generated_clock PLL create_generated_clock PLL derive_pll_clocks PLL PLL PLL Quartus II TimeQuest Warning:The master clock for this clock assignment could not be derived. Clock:<name of PLL output clock pin name> was not created Altera Corporation

43 SDC derive_pll_clocks PLL derive_pll_clocks derive_pll_clocks SDC PLL create_generated_clocks write_sdc -expand derive_pll_clock SDC PLL derive_pll_clocks create_generated_clock PLL SDC derive_pll_clocks SDC create_generated_clock PLL derive_pll_clocks LVDSLVDS 7 27 PLL PLL pll_inclk pll_inst reg1 reg2 dataout derive_pll_clocks PLL derive_pll_clocks Info: Info:Deriving PLL Clocks: Info:create_generated_clock -source pll_inst altpll_component pll inclk[0] -divide_by 2 -name pll_inst altpll_component pll CLK[0] pll_inst altpll_component pll clk[0] Info: Altera Corporation 7 43

44 Quartus II Volume 3 pll_inst altpll_component pll inclk[0] PLL PLL PLL pll_inst altpll_component pll clk[0] PLL PLL 1 inclk[0] 1 inclk[1] set_clock_groups -exclusive PLL create_clock -period 5 [get_ports pll_inclk] pll_inst altpll_component pll inclk[0] PLL PLL PLL Quartus II TimeQuest Quartus II TimeQuest 1 GHz derive_clocks -period 1 create_clock create_generated_clock derive_clocks 7 44 Altera Corporation

45 Quartus II TimeQuest 2 set_clock_groups 7 13 set_clock_groups set_clock_groups set_clock_groups [-asynchronous -exclusive] -group <clock name> [-group <clock name>] [-group <clock name>] set_clock_groups set_clock_groups -asynchronous -exclusive -group <clock name> to-1 MUX <clock name> exclusive 2 A 25 MHz 50 MHz 2 set_ clock_groups -exclusive Altera Corporation 7 45

46 Quartus II Volume 3 25 MHz 50 MHz exclusive create_clock -period 40 -name clk_a [get_ports {port_a}] create_clock -add -period 20 -name clk_b [get_ports {port_a}] set_clock_groups -exclusive -group {clk_a} -group {clk_b} -group TimeQuest -group asynchronous asynchronous clk_a clk_b clk_c 3 clk_a clk_b clk_c clk_a clk_b 7 15 clk_a clk_b clk_c asynchronous 1 set_clock_groups -asynchronous -group {clk_a clk_b} -group {clk_c} asynchronous 2 set_clock_groups -asynchronous -group {clk_c} clk_c 1 TimeQuest 7 46 Altera Corporation

47 7 17 set_clock_groups set_false_path set_clock_groups # A C B D set_clock_groups -exclusive -group {A C} -group {B D} # set_false_path -from [get_clocks A] -to [get_clocks B] set_false_path -from [get_clocks A] -to [get_clocks D] set_false_path -from [get_clocks C] -to [get_clocks B] set_false_path -from [get_clocks C] -to [get_clocks D] set_false_path -from [get_clocks B] -to [get_clocks A] set_false_path -from [get_clocks B] -to [get_clocks C] set_false_path -from [get_clocks D] -to [get_clocks A] set_false_path -from [get_clocks D] -to [get_clocks C] create_clock create_generated_clock 2 set_clock_latency -source set_clock_latency 7 18 set_ clock_latency Altera Corporation 7 47

48 Quartus II Volume set_clock_latency set_clock_latency -source [-clock <clock_list>] [-rise -fall] [-late -early] <delay> <targets> 7 11 set_clock_latency set_clock_latency -source -clock <clock list> -rise -fall -late -early <delay> <targets> Quartus II TimeQuest set_clock_latency set_clock_uncertainty Quartus II TimeQuest 7 48 Altera Corporation

49 set_clock_uncertainty 7 19 set_clock_uncertainty set_clock_uncertainty set_clock_uncertainty [-rise_from <rise from clock> -fall_from <fall from clock> -from <from clock>] [-rise_to <rise to clock> -fall_to <fall to clock> -to <to clock>] [-setup -hold] <value> 7 12 set_clock_uncertainty set_clock_uncertainty -from <from clock> -rise_from <rise from clock> -fall_from <fall from clock> -to <to clock> -rise_to <rise to clock> -fall_to <fall to clock> -setup -hold <value> from clock rise-from clock fall-from clock to clock rise-to clock fall-to clock setup hold derive_clock_uncertainty I/O 7 20 derive_clock_uncertainty derive_clock_uncertainty derive_clock_uncertainty [-overwrite] [-add] Altera Corporation 7 49

50 Quartus II Volume derive_clock_uncertainty derive_clock_uncertainty -overwrite -add derive_clock_uncertainty Quartus II TimeQuest set_clock_uncertainty derive_clock_uncertainty set_clock_uncertainty clka clkb derive_clock_uncertainty set_clock_uncertaintyderive_clock_uncertainty -overwrite remove_clock_uncertainty -add derive_clock_uncertainty derive_clock_uncertainty I/O derive_clock_uncertainty 7 50 Altera Corporation

51 FPGA PLL Source Register Destination Register data_in D Q D Q data_out PLL clk0 FPGA PLL Source Register Destination Register data_in D Q D Q data_out clk_in PLL clk0 I/O I/O I/O FPGA FPGA I/O 7 30 I/O Altera Corporation 7 51

52 Quartus II Volume I/O reg1 data_in D Q data_out clk_in I/O set_input_delay set_ output_delay set_input_delay set_output_delay PLL derive_ clock_uncertainty I/O set_input_delay set_output_delay derive_clock_uncertainty I/O I/O 7 31 I/O I/O External Device Altera FPGA D reg1 Q data_in D reg1 Q clk_in 100 MHz 7 52 Altera Corporation

53 I/O I/O SDC I/O SDC # create_clock period 10 name clk_in [get_ports clk_in] # create_clock period 10 name virt_clk_in # # # set_input_delay clock clk_in <delay_value> [get_ports data_in] set_input_delay clock virt_clk_in <delay value> [get_ports data_in] I/O Quartus II TimeQuest SDC Quartus II TimeQuest FPGA Quartus II TimeQuest Set Input Delay set_input_delay I/O Set Input Delay External Device Altera Device Oscillator Altera Corporation 7 53

54 Quartus II Volume 3 set_input_delay 7 22 set_input_delay set_input_delay set_input_delay -clock <clock name> [-clock_fall] [-rise -fall] [-max -min] [-add_delay] [-reference_pin <target>] [-source_latency_included] <delay value> <targets> 7 14 set_input_delay set_input_delay -clock <clock name> -clock_fall -rise -fall -max -min -add_delay -reference_pin <target> -source_latency_ included <delay value> <targets> 7 54 Altera Corporation

55 I/O max min -rise -fall min/max rise/fall -clock -clock_fall -reference_pin -clock_fall -reference_pin -add_delay -add_delay -min -max -rise -fall Set Output Delay set_output_delay set_output_delay Altera Device External Device Oscillator Altera Corporation 7 55

56 Quartus II Volume set_output_delay set_output_delay set_output_delay -clock <clock name> [-clock_fall] [-rise -fall] [-max -min] [-add_delay] [-reference_pin <target>] <delay value> <targets> 7 15 set_output_delay set_output_delay -clock <clock name> -clock_fall -rise -fall -max -min -add_delay -reference_pin <target> -source_latency_included <delay value> <targets> max min 7 56 Altera Corporation

57 min/max rise/fall 1 -clock_fall -clock_fall -add_delay -add_delay -min -max -rise -fall Quartus II TimeQuest Altera Corporation 7 57

58 Quartus II Volume 3 set_false_path 7 24 set_false_path set_false_path set_false_path [-fall_from <clocks> -rise_from <clocks> -from <names>] [-fall_to <clocks> -rise_to <clocks> -to <names>] [-hold] [-setup] [-through <names>] <delay> 7 16 set_false_path set_false_path -fall_from <clocks> -fall_to <clocks> -from <names> -hold -rise_from <clocks> -rise_to <clocks> -setup -through <names> -to <names> <delay> <names> <clocks> <names> <clocks> <names> <names> <names> <clocks> <names> <clocks> <names> <names> <names> <names> 7 58 Altera Corporation

59 2 -from-to set_min_delay set_min_delay set_min_delay set_min_delay [-fall_from <clocks> -rise_from <clocks> -from <names>] [-fall_to <clocks> -rise_to <clocks> -to <names>] [-through <names>] <delay> 7 17 set_min_delay set_min_delay -fall_from <clocks> -fall_to <clocks> -from <names> -rise_from <clocks> -rise_to <clocks> -through <names> -to <names> <delay> <names> <clocks> <names> <clocks> <names> <names> <names> <clocks> <names> <clocks> <names> <names> <names> <names> Altera Corporation 7 59

60 Quartus II Volume 3 2 -from-to set_min_delayset_output_delay Clock set_min_delay 0 set_output_delay set_output_ delay set_max_delay 7 26 set_max_delay set_max_delay set_max_delay [-fall_from <clocks> -rise_from <clocks> -from <names>] [-fall_to <clocks> -rise_to <clocks> -to <names>] [-through <names>] <delay> 7 60 Altera Corporation

61 7 18 set_max_delay set_max_delay -fall_from <clocks> -fall_to <clocks> -from <names> -rise_from <clocks> -rise_to <clocks> -through <names> -to <names> <delay> <names> <clocks> <names> <clocks> <names> <names> <names> <clocks> <names> <clocks> <names> <names> <names> <names> 2 -from-to set_max_delay set_output_delay Clock Altera Corporation 7 61

62 Quartus II Volume 3 set_max_delay 0 set_output_delayset_ output_delay Quartus II TimeQuest 2 2 -start -end set_multicycle_path 7 27 set_multicycle_path set_multicycle_path set_multicycle_path [-end] [-fall_from <clocks> -rise_from <clocks> -from <names>] [-fall_to <clocks> -rise_to <clocks> -to <names>] [-hold] [-setup] [-start] [-through <names>] <path multiplier> 7 62 Altera Corporation

63 7 19 set_multicycle_path set_multicycle_path -fall_from <clocks> -fall_to <clocks> -from <names> -hold -setup -rise_from <clocks> -rise_to <clocks> -start -end -through <names> -to <names> <path multiplier> <names> <clocks> <names> <clocks> <names> <names> <names> <clocks> <names> <clocks> <names> <names> <names> <names> 2 -from-to set_multicycle_path 7 34 src_clk 10 ns dst_clk 5ns Altera Corporation 7 63

64 Quartus II Volume reg reg data_in src_clk D Q D Q data_out dst_clk ns 0ns setup hold set_multicycle_path 7 20 Quartus II TimeQuest set_multicycle_path -setup -end set_multicycle_path -setup -start set_multicycle_path -hold -end set_multicycle_path -hold -start 7 64 Altera Corporation

65 7 36 5ns 10 ns # 2 set_multicycle_path -from [get_clocks src_clk] -to [get_clocks dst_clk] -setup -end 2 new setup default setup Quartus II TimeQuest Quartus II TimeQuest remove_clock [-all] [<clock list>] remove_clock_groups -all remove_clock_latency -source <targets> remove_clock_uncertainty -from <from clock> -to <to clock> remove_input_delay <targets> remove_output_delay <targets> reset_design <clock list> -all <targets> <from clock> <to clock> <targets> <targets> Altera Corporation 7 65

66 Quartus II Volume 3 Quartus II TimeQuest Quartus II TimeQuest report_timing report_timing 7 28 report_timing report_timing report_timing [-append] [-detail <summary path_only path_and_clock full_path>] [-fall_from_clock <names>] [-fall_to_clock <names>] [-false_path] [-file <name>] [-from <names>] [-from_clock <names>] [-hold] [-less_than_slack <slack limit>] [-npaths <number>] [-nworst <number>] [-pairs_only] [-panel_name <name>] [-recovery] [-removal] [-rise_from_clock <names>] [-rise_to_clock <names>] [-setup] [-show_routing] [-stdout] [-through <names>] [-to <names>] [-to_clock <names>] 7 66 Altera Corporation

67 7 22 report_timing report_timing / -append -detail <summary path_only path _and_clock full_path> -fall_from_clock <names> -fall_to_clock <names> -false_path -file <name> -hold -less_than_slack <slack limit> -npaths <number> -nworst <number> -panel_name <names> -panel_name <names> -pairs_only -recovery -removal -rise_from_clock <names> -rise_to_clock <names> -setup -show_routing -file Path Only: Summary: Path and Clock: Full Path: <names> from_clock fall_from_clock rise_from_clock <names> to_clock fall_to_clock rise_to_clock <name> <slack limit> Reports <names> from_clock fall_from_clock rise_from_clock <names> to_clock fall_to_clock rise_to_clock Altera Corporation 7 67

68 Quartus II Volume report_timing / -stdout -through <names> -to <names> -to_clock <names> stdout 7 29 report_timing -from_clock clk_async -to_clock clk_async -setup -npaths report_timing Info: =================================================================== Info: To Node :dst_reg Info: From Node :src_reg Info: Latch Clock :clk_async Info: Launch Clock :clk_async Info: Info: Data Arrival Path: Info: Info: Total (ns) Incr (ns) Type Node Info: ========== ========= == ==== ========================== Info: launch edge time Info: R clock network delay Info: utco src_reg Info: RR CELL src_reg regout Info: RR IC dataout datain Info: RR CELL dst_reg Info: Info: Data Required Path: Info: Info: Total (ns) Incr (ns) Type Node Info: ========== ========= == ==== ========================== Info: latch edge time Info: R clock network delay Info: utsu dst_reg Info: Info: Data Arrival Time : Info: Data Required Time : Info: Slack : Info: ========================================================== 7 68 Altera Corporation

69 report_timing 7 23 report_timing Total Incr RF Type Node Total Incr RF Type Fanout Location Element R F RR RF FR FF 7 24 FPGA 7 24 report_timing CELL FPGA CELL ALM DSP I/O COMP PLL IC µt CO clock-to-out µt SU µt H i EXT o EXT Altera Corporation 7 69

70 Quartus II Volume 3 report_metastability report_metastability MTBF report_metastability report_metastabiity [-append] [-file <name>] [-panel_name <name>] [-stdout] 7 25 report_metastability report_metastability -append -file <name> -panel_name <name> -stdout -file stdout report_metastability MTBF MTBF MTBF MTBF 25 MTBF 12.5% % 7 70 Altera Corporation

71 TimeQuest set_input_delay TimeQuest set_max_delay set_max_delay set_max_delay set_input_delay max set_max_delay <t SU requirement> set_input_delay -max <latch launch t SU requirement> TimeQuest Metastability Analysis Synchronization Register Chain Length Metastability Analysis TimeQuest Metastability Analysis AUTO Altera Corporation 7 71

72 Quartus II Volume 3 Metastability Analysis Metastability Analysis ON AUTO 1 OFF Metastability Analysis Quartus II Settings Timing Analysis Settings TimeQuest Timing Analyzer Metastability Analysis Metastability Analysis Assignment Editor Metastability Analysis Assignment Editor Analyze Metastability OFF Analyze Metastability 7 72 Altera Corporation

73 Synchronization Register Chain Length Synchronization Register Chain Length Quartus II Synchronization Register Chain Length 2 2 Synchronization Register Chain Length 2 Synchronization Register Chain Length Settings Analysis & Synthesis More Settings More Settings Synchronization Register Chain Length Assignment Editor Synchronization Register Chain Length 3 2 report_clock_transfers report_clock_transfers 2 2 report_clock_transfers Altera Corporation 7 73

74 Quartus II Volume report_clock_transfers report_clock_transfers report_clock_transfers [-append] [-file <name>] [-hold] [-setup] [-stdout] [-recovery] [-removal] [-panel_name <name>] 7 27 report_clock_transfers report_clock_transfers -append -file -file <name> <name> -hold -setup -stdout stdout -recovery -removal -panel_name <name> report_clocks report_clocks 7 74 Altera Corporation

75 7 32 report_clocks report_clocks report_clocks [-append] [-desc] [-file <name>] [-stdout] [-panel_name <name>] 7 28 report_clocks report_clocks -append -file -file <name> <name> -desc -stdout stdout -panel_name <name> report_min_pulse_width report_min_pulse_width High Low report_min_ pulse_width High Low report_min_pulse_width RAM DSP I/O / -reference_pin Altera Corporation 7 75

76 Quartus II Volume 3 report_min_pulse_width I/O report_min_pulse_width I/O -reference_pin High 2 Low 7 33 report_min_pulse_width report_min_pulse_width report_min_pulse_width [-append] [-file <name>] [-nworst <number>] [-stdout] [<targets>] [-panel_name <name>] 7 29 report_min_pulse_width report_min_pulse_width -append -file <name> -nworst <number> -stdout -targets -panel_name <name> 1 stdout 7 76 Altera Corporation

77 report_net_timing report_net_timing 7 34 report_net_timing report_net_timing report_net_timing [-append] [-file <name>] [-nworst_delay <number>] [-nworst_fanout <number>] [-stdout] [-panel_name <name>] 7 30 report_net_timing report_net_timing -append -file -file <name> <name> -nworst_delay <number> -nworst_fanout <number> <number> <number> -stdout stdout -panel_name <name> Altera Corporation 7 77

78 Quartus II Volume 3 report_sdc report_sdc SDC 7 35 report_sdc report_sdc report_sdc [-ignored] [-append] [-file] [-stdout] [-panel_name <name>] 7 31 report_sdc report_sdc -ignored -append -file <name> -stdout -panel_name <name> -file <name> stdout report_ucp report_ucp 7 36 report_ucp report_ucp report_ucp [-append] [-file <name>] [-hold] [-setup] [-stdout] [-summary] [-panel_name <name>] 7 78 Altera Corporation

79 7 32 report_ucp report_ucp -append -file <name> -hold -setup -stdout -summary -panel_name <name> -file <name> stdout 7 33 Quartus II TimeQuest Tasks Tcl / Task Report Setup Summary Report Hold Summary Report Recovery Summary Report Removal Summary Tcl create_timing_summary -setup create_timing_summary -hold create_timing_summary -recovery create_timing_summary -removal Report Clocks report_clocks Report Clock Transfers report_clock_transfers Report SDC report_sdc SDC Report Unconstrained Paths report_ucp Report Timing report_timing Report Net Timing report_net_timing Altera Corporation 7 79

80 Quartus II Volume Tasks Tcl / Task Report Minimum Pulse Width Create Slack Histogram Tcl report_min_pulse_width create_slack_histogram report_path report_path 7 37 report_path report_path report_path [-append] [-file <name>] [-from <names>] [-npaths <number>] [-stdout] [-through] [-to <names>] [-panel_name <name>] 7 34 report_path report_path -append -file <name> -from <names> -npaths <number> -stdout -through <name> -to <names> -panel_name <name> -file <name> stdout 7 80 Altera Corporation

81 report_bottleneck report_bottleneck1, report_bottleneck report_bottleneck report_bottleneck [-cmetric <cmetric_name>] [-details] [-metric <default tns num_paths num_fpaths num_fanins num_fanouts>] [-panel <panel_name>] [-stdout] [<paths>] report_bottleneck 1,000 -metric num_fanouts -metric tns get_timing_paths report_bottleneck 7 35 report_bottleneck report_bottleneck / -cmetric <cmetric_name> -details -metric <default tns num_paths num_fpaths num_fanins num_fanouts> -panel <panel_name> Altera Corporation 7 81

82 Quartus II Volume report_bottleneck / -stdout <paths> stdout 7 39 report_bottleneck report_bottleneck # set paths [ get_timing_paths -npaths setup ] # proc report_bottleneck_custom_metric {arg} { # upvar $arg metric set rating $metric(num_fanins) return $rating } # report_bottleneck -cmetric report_bottleneck_custom_metric -panel "Timing Analysis Bottleneck Report - Custom" $paths report_datasheet report_datasheet tsu thclock-to-output tco clock-to-output mintco tpd mintpd 7 40 report_datasheet report_datasheet report_datasheet [-append] [-file <name>] [-stdout] [panel_name <name>] 7 82 Altera Corporation

83 7 36 report_datasheet report_datasheet -append -file <name> -stdout -panel_name <name> -file <name> stdout 1 t SU t H t CO t PD mint CO mint PD report_rskm report_rskm LVDS 7 41 report_rskm report_rskm report_rskm [-append] [-file <name>] [-panel_name <name>] [-stdout] 7 37 report_rskm report_rskm -append -file <name> -panel_name <name> -stdout file <name> stdout Altera Corporation 7 83

84 Quartus II Volume 3 RSKM LVDS RSKM TUISW RCCS 12 (12) ( TUI SW RCCS) RSKM = LVDS 1/f MAX LVDS RCCS LVDS RCCS TCCS RCCS RCCS report_tccs report_tccs LVDS 7 42 report_tccs report_tccs report_tccs [-append] [-file <name>] [-panel_name <name>] [-quiet] [-stdout] 7 84 Altera Corporation

85 7 38 report_tccs report_tccs -append -file <name> -panel_name <name> -quiet -stdout file <name> LVDS stdout TCCS t CO report_path report_path report_path report_path report_path [-append] [-file <name>] [-from <names>] [-min_path] [-npaths <number>] [-nworst <number>] [-panel_name <name>] [-stdout] [-summary] [-through <names>] [-to <names>] Altera Corporation 7 85

86 Quartus II Volume report_path report_path -append -file <name> -from <names> -min_path -npaths <number> -nworst <number> -panel_name <name> -stdout -summary -through <names> -to <names> -file <name> <names> <names> stdout 1 <names> <names> <names> <names> data_in_a data_in_b reg1 D Q and2 reg2 D Q data_out clk_i PLL c0 c1 clk_out 7 86 Altera Corporation

87 7 44 report_path -from [get_pins {reg1 regout}] -to [get_pins \ {reg2 datain}] -npaths 1 -panel_name "Report Path" stdout report_path Info: =============================================================== Info: From Node :reg1 regout Info: To Node :reg2 datain Info: Info: Path: Info: Info: Total (ns) Incr (ns) Type Element Info: ========== ========= == ==== =================== Info: reg1 regout Info: RR IC and2 datae Info: RR CELL and2 combout Info: RR IC reg2 datain Info: Info: Total Path Delay : Info: =============================================================== report_path Info:Report Path:No paths were found report_path -from [get_ports data_in_a] -to \ [get_pins {reg2 regout}] -npaths check_timing check_timing check_timing 7 46 check_timing Altera Corporation 7 87

88 Quartus II Volume check_timing check_timing [-append] [-file <name>] [-include <check_list>] [-stdout] [-panel_name <name>] 7 40 check_timing check_timing -append -file <name> -include -stdout -panel_name <name> -file <name> <check_list> 7 41 stdout / no_clock multiple_clock generated_clock no_input_delay no_output_delay 1 1 clk2 clk1 clk1 clk Altera Corporation

89 7 41. / partial_input_delay partial_output_delay rise-min fall-min risemax fall-max rise-min fall-min risemax fall-max reference_pin reference_pin set_input_delay set_output_delay reference_pin set_input_delay/set_ output_delay reference_ pin reference_ pin reference_ pin latency_override loops latches Quartus II TimeQuest 7 47 check_timing check_timing # create_clock -name clk -period waveform { } \ [get_ports clk] set_input_delay -clock clk2 1.5 [get_ports in*] set_output_delay -clock clk 1.6 [get_ports out*] set_false_path -from [get_keepers in] -through [get_nets r1] -to \ [get_keepers out] # check_timing -include {loops latches no_input_delay partial_input_delay} Altera Corporation 7 89

90 Quartus II Volume 3 report_clock_fmax_summary report_clock_fmax_summary f MAX f MAX f MAX f MAX f MAX 7 48 report_clock_fmax_summary report_clock_fmax_summary report_clock_fmax_summary [-append] [-file <name>] [-panel_name <name>] [-stdout] 7 42 report_clock_fmax_summary report_clock_fmax_summary -append -file <name> -stdout -panel_name <name> -file <name> stdout 7 90 Altera Corporation

91 f MAX f MAX Restricted f MAX Clock Name Note f MAX f MAX Restricted f MAX I/O I/O RAM DSP f MAX Clock Name Note create_timing_summary TNS Total Negative Slack Total Negative Slack 7 49 create_timing_summary create_timing_summary create_timing_summary [-append] [-file <name>] [-hold] [-panel_name <name>] [-recovery] [-removal] [-setup] [-stdout] Altera Corporation 7 91

92 Quartus II Volume create_timing_summary create_timing_summary -append -file <name> -hold -panel_name <name> -recovery -removal -setup -stdout -file <name> stdout TimeQuest TimeQuest set_operating_conditions create_timing_netlist create_ timing_netlist Altera Corporation

93 7 50 set_operating_conditions set_operating_conditions set_operating_conditions [-model <fast slow>] [-speed <speed grade>] [-temperature <value in ºC>] [-voltage <value in mv>] [<operating condition Tcl object>] 7 45 set_operating_conditions set_operating_conditions -model <fast slow> -speed <speed grade> -temperature <value in ºC> -voltage <value in mv> <operating condition Tcl object> Tcl Tcl model speed temperature voltage Tcl model -speed -temperature -voltage Altera Corporation 7 93

94 Quartus II Volume Stratix III 4 slow slow fast Cyclone III 7 slow slow fast Stratix II 4 slow fast Cyclone II 6 slow fast mv Tcl 4_slow_1100mv_85c 4_slow_1100mv_0c MIN_fast_1100mv_0c 7_slow_1200mv_85c 7_slow_1200mv_0c MIN_fast_1200mv_0c N/A N/A 4_slow MIN_fast N/A N/A 6_slow MIN_fast get_available_operating_conditions 7 51 Stratix III 1100 mv 85 C set_operating_conditions -model slow -temperature 85 -voltage Tcl Tcl set_operating_conditions 4_slow_1100mv_85c 7 94 Altera Corporation

95 I/O Quartus II TimeQuest I/O I/O I/O Settings TimeQuest Timing Analyzer on off Advanced I/O Timing - force_dat Quartus II TimeQuest Tcl create_timing_netlist -force_dat I/O -force_dat create_timing_netlist Tasks Create Timing Netlist I/O Quartus II Volume 2 I/O Quartus II TimeQuest *? * reg* Quartus II TimeQuest reg 0 1 reg1 reg[2] regbank reg12bank Altera Corporation 7 95

96 Quartus II Volume 3? 1 reg? Quartus II TimeQuest reg 1 reg1 rega reg4 get_cells get_pins 3 -hierarchical -compatibility Quartus II TimeQuest <absolute full cell name> <pin suffix> get_cells get_pins 1 * * * 2 get_cells get_pins -hierarchical <short cell name> <pin name> get_cells -hierarchical get_pins get_cells get_pins -compatibility Quartus II 7 96 Altera Corporation

97 foo foo bar foo dataa foo datab foo bar datac foo bar datad get_pins * dataa foo dataa get_pins * datac <empty> get_pins * * datac foo bar datac get_pins foo* * foo dataa, foo datab get_pins -hierarchical * * datac <empty> (1) get_pins -hierarchical foo * foo dataa, foo datab get_pins -hierarchical * datac foo bar datac get_pins -hierarchical foo * datac <empty> (1) get_pins -compatibility * datac foo bar datac get_pins -compatibility * * datac foo bar datac 7 47 : (1) * * <empty> reset_design Altera Corporation 7 97

98 Quartus II Volume 3 TimeQuest Quartus II TimeQuest GUI View Locate Path Locate From Node To Node Locate Path Locate Required Path 1 Locate Locate Path Locate Chip Planner Technology Map Viewer Resource Property Editor Locate Path Critical Path Settings Chip Planner Critical Path Settings TimeQuest locate Console locate Chip Editor Critical Path Settings Resource Property Editor Technology Map Viewer 7 53 locate 7 98 Altera Corporation

99 7 53. locate locate [-chip] [-color <black blue brown green grey light_grey orange purple red white>] [-cps] [-label <label>] [-rpe] [-tmv] <items> 7 48 locate locate -chip -color <black blue brown green grey light_grey orange pur ple red white> -cps -label <label> -rpe -tmv <items> Chip Planner Chip Planner Critical Path Settings Resource Property Editor Technology Map Viewer 7 54 TimeQuest Chip Editor 10 Technology Map Viewer TimeQuest # Chip Editor 10 # locate [get_path -npaths 10] -chip # Tech Map Viewer locate [get_ports data*] -tmv Altera Corporation 7 99

100 Quartus II Volume 3 TimeQuest GUI Quartus II TimeQuest GUI GUI Quartus II View Tasks Console Report Constraints Name Finder Target SDC TimeQuest GUI Altera Corporation

101 TimeQuest GUI Quartus II Quartus II Compilation Report Quartus II TimeQuest Settings TimeQuest Quartus II TimeQuest SDC files to include in the project Enable Advanced I/O Timing Enable multicorner timing analysis during compilation Report worst-case paths during compilation Tcl Script File for customizing report during compilation SDC I/O 7 49 Compilation Report Quartus II TimeQuest View View View 7 39 Report Summary (Setup) View Altera Corporation 7 101

102 Quartus II Volume Summary (Setup) View : View View View View View View Altera Corporation

103 TimeQuest GUI View View View : View 7 42 Altera Corporation 7 103

104 Quartus II Volume Tasks Tasks Tasks Open Project Set Operating Conditions Reset Design Netlist Setup Reports Tasks Tcl Console Synopsys Design Constraints Quartus II TimeQuest Open Project Quartus II TimeQuest Quartus II GUI Altera Corporation

105 TimeQuest GUI Quartus II TimeQuest SDC SDC Quartus II TimeQuest Write SDC File Quartus II TimeQuest SDC Netlist Setup Netlist Setup Create Timing Netlist Read SDC File Update Timing Netlist 3 Create Timing Netlist Quartus II TimeQuest Quartus II TimeQuest Quartus II TimeQuest Read SDC File Read SDC File <current revision>.sdc read_sdc SDC Update Timing Netlist SDC Altera Corporation 7 105

106 Quartus II Volume 3 Reports Reports Reports Report f MAX Summary Report Setup Summary Report Hold Summary Report Recovery Summary Report Removal Summary Report Clocks Report Clock Transfers Report Minimum Pulse Width Report SDC Report Unconstrained Paths Report Ignored Constraints Report Datasheet f MAX SDC SDC SDC Macros Macros Quartus II TimeQuest Report All Summaries Report Top Failing Paths Create All Clock Histograms Altera Corporation

107 TimeQuest GUI 7 51 Macros Macros Report All Summaries Report Top Failing Paths Create All Clock Histograms Report All I/O Timings Report All Core Timings Report Setup Summary Report Hold Summary Report Recovery Summary Report Removal Summary Minimum Pulse Width Create Slack Histogram Console Console Quartus II TimeQuest Tcl Console Console History 2 Console Console Synopsys Tcl Console Tasks Tcl History Synopsys Tcl History Rerun Console History Tcl Tcl Report Report Tasks Report View Altera Corporation 7 107

108 Quartus II Volume 3? Constraints Constraints Edit Constraint menu Constraints Create Clock Create Generated Clock Set Clock Latency Set Clock Uncertainty Set Clock Groups Remove Clock Create Clock 7 43 Create Clock Create Clock Constraints Set False Path Set Multicycle Path Set Maximum Delay Altera Corporation

109 TimeQuest GUI Set Minimum Delay SDC OK SDC Quartus II TimeQuest Console Constraints SDC Write SDC File Quartus II TimeQuest Constraints Generate SDC File from QSF Read SDC File Write SDC File Generate SDC File from QSF QSF Quartus II Quartus II TimeQuest SDC Tcl <current revision>.sdc Generate SDC File from QSF Quartus II Volume 3 Switching to the Quartus II TimeQuest Timing Analyzer Generate SDC File from QSF QSF SDC QSF SDC SDC Read SDC File <current revision>.sdc Write SDC File Quartus II TimeQuest SDC Altera Corporation 7 109

110 Quartus II Volume 3 Name Finder Name Finder Quartus II TimeQuest GUI Name Finder Name Finder Collections Collection API get_cells get_clocks get_keepers get_nets get_nodes get_pins get_ports get_registers API 7 29 Filter Case-insensitive Hierarchical Compatibility mode 7 95 Name Finder SDC command Name Finder Altera Corporation

111 TimeQuest GUI Name Finder Target TimeQuest GUI View View View Altera Corporation 7 111

112 Quartus II Volume Target View Pane Window State View Partially Filled Red Circle Fully Filled Red Circle Empty Circle SDC TimeQuest GUI SDC SDC SDC SDC SDC Constraints Constraints SDC Altera Corporation

113 Quartus II TimeQuest Quartus II TimeQuest SDC Quartus II Volume 2 I/O Management SDC and TimeQuest API Reference Manual Quartus II Volume 4 Volume 4: SOPC Builder Quartus II Volume 3 Quartus II TimeQuest Timing Analyzer TimeQuest Quick Start Tutorial Altera Corporation 7 113

114 Quartus II Volume / v v7.2.0 Quartus II v8.0 Quartus II 7 27 Quartus II v8.0 TimeQuest 7 31 SDC ADoQS report_rskm RSKM report_clock_fmax_summary derive_clock_uncertainty 7 49 [-dtw] [-add] 7 70 report_metastability 7 83 report_rskm RSKM 7 98 Quartus II v7.2 Compilation Flow with TimeQuest Guidelines Timing Analysis OverviewSpecify Design Timing Requirements Clock as Data Quartus II v Altera Corporation

115 7 53. / v v v v v6.0.0 Quartus II v Timing Reports report_path report_timing 6-11 Derive Clock Uncertainty 6 40 report_rskm 6 69 report_tccs 6 69 report_path 6 70 Fast Timing Model Analysis Multi-Corner Analysis Quartus II 7.0 Quartus II v6.1 Specifying Clock Requirements Specifying Input and Output Port RequirementsReporting Getting Started Create Clock Create Generated Clock / SDC GUI SDC Quartus II v6.0.1 report_clock_transfers 6-15 Quartus II v7.2 Quartus II v6.1 Altera Corporation 7 115

116 Quartus II Volume Altera Corporation