km sr ev ev AGASA.

Transcription

1

2 km sr ev ev AGASA.

3 . EHECR.... EHECR TA PMT Signal Digitizer and Finder SDF Utah... A

4 B B. Pre AMP... B. SDF filter... C SDF

5 Penzias,Wilson WMAP.K [] ev ( EHECR, Extremely High Energy Cosmic Ray ) [],[] Greisen,Zatsepin,Kuzmin GZK p γ () N π EHECR EHECR EHECR. ev EHECR ev E/(dE/dx) EHECR ev γ γ e e. ev ev ev EHECR AGASA,HiRes,Auger AGASA (.) ev AGASA GZK HiRes GZK AGASA ev EHECR AGASA GZK AGASA.

6 .: EHECR, AGASA[] Hires [] Hires (Preliminarily)[] Auger(Preliminarily)[] [] AGASA EHECR GZK EHECR AGASA GZK ( TA) GZK EHECR EHECR EHECR EHECR Signal Digitizer and Finder(SDF) FD SDF

7 . EHECR EHECR ev [] ev. pc. pc EHECR [].: x loss = E/( de/dx) G G.K. µg

8 ( B x loss (E) = E σ T cγ β µ ) =. E B [pc] (.) E [ev] B [µg] µ σ T c β c γ =/ β µg ev.pc ev. pc EHE l(e) = Ei E x loss (ɛ) dɛ (.) ɛ E i.. Energy [ev] p γ Propagation Distance [Mpc].: EHECR. ev Mpc. ev Mpc ev Mpc Gpc Mpc ev [].

9 .. EHECR SOURCE kpc Number of Events [arbitrary scale] Fe Mpc Mpc Nuclei Proton Mpc Mpc log ( ENERGY [ev] ) log ( ENERGY [ev] ).: (). ev ev. EHECR EHECR.. EHECR. EHECR. ev

10 ev Magnetic Field Strength G Neutron Stars G LHC TEVATRON SppS White Dwarfs AGNs Sunspots GRBs ev at β = ev at β = / G G Interplanetary space SNRs Galactic Halo Radio Galaxy Galactic Cluster km km AU Size pc kpc Mpc Gpc.: AGN SNR GRB Gamma Ray Burst EHECR ev (Active Galactic Nuclei,AGN) ev (radio hotspot) hotspot AGN AGASA AGN EHECR AGN ev

11 .... EHECR (Super Heavy Relic Particles,SHR) EHECR SHR. SHR EHECR EHECR EHECR SHR (Topological Defects,TD) EHECR TD Z EHECR diffuse ev mb. EHECR /e X. g/cm /X X

12 ɛ MeV [] [ (. X N e (E,X) = ln(e/ɛ ) exp )] λ rl ln s, (.) s = X X λ rl ln(e/ɛ ) N e (E,X) E X λ rl s s< s > θ (E) (.) θ (E) = E S /E (.) E E S =[MeV] ( ) R α ( ρ e (R) = N e C R ) (η α), (.) R m C = R m R m Γ(η α) πγ( α)γ(η ), = θ (ɛ ) X = E s ɛ X (.) [] α, η α s, η. s π γnm µ ± EHECR ( )( E Xmax X N e (E,X) =S exp ɛ λ at X max λ at ( E S =.(. ln [TeV] X max = log ( E [ev] ) Xmax ) λ at exp ( Xλat, (.) ), (.) ) [g/cm ] (.) [] X EHECR [g/cm ] λ at [g/cm ] GaisserHillas.

13 ... EHECR. N e. m. /m MeV GeV. MeV.: [].MeV [] MeV m

14 TeV X max m X max m km

15 TA TA km HiRes AGASA. ( FD,Fluorescence Detector ) ( SD Surface Detector ) TA mm HiRes FD,m SD FD. TA. TA.km o km sr.m PMT PhotoMultiplier Tube PMT MHz ADC GPS (Motorola M) ns

16 TA.: TA SD FD FD.GHz.km kbps W.: TA

17 ... TA FD HiRes FD [m] [km] Black Rock Mesa(TA).N.W Long Ridge(TA).N.W. Drum Mountain(HiRes).N.W..: TA ev km. FD. m LAN FD.: FD

18 TA (.) FD (.),mm, m (Schott Tempax glass) Al O TA mm...: FD.: FD ( ) ( )

19 .. PMT. PMT x PMT( R). FD PMT PMT.. PMT PMT.mm (Schott BG) nm nm BG. (.) nm ( ) (. ).: FD ( ) PMT( ) ) quantum efficiency wave length (nm).: BG ( ) PMT ( ) mm ( ) TAFD PMT PMT YAP p.e.(photo electron)/µs..µa µa( V)

20 TA. PMT Ω PMT Ω PMT.: PMT

21 Utah. FD FD ns km GPS ns. MHz. PMT DC DC AC PMT PMT AC AC TA PMT. (PMT ) PMT m m PMT. PMT PMT. FD kw TA PMT Signal Digitizer and Finder SDF ) Track Finder( TF) Central Trigger Distributor( CTD ) VME ( SBS model, bit) (HVPS,High Voltage Power Supply and Distributor)

22 TA PC SDF,TF,CTD U VME bitvme bus KEKU VME bus U VME J,J J U VME J,J ±.V,V J J J,J LVDS bit U VME J,J bit P.MBps(Mega Byte per second) nonblock DMA MBps HVPS VMEU VME VME PMT HV V V LAN PC. FD A.: FD

23 .... FD. PMT PMT C [] FD PMT.. TA. ns FD. FD PMT Ω AD ( ) m SDF (Signal Digitizer and Finder) SDF PMT ±V SDF (WFSA,Wave Form Shaping Amplifier ) ( ) R(t) R(t) = te τ t τ (.) τ. B τ WFSA.V FADC(Flash Analog Digital Converter) V WFSA V WFSA WFSA WFSA WFSA WFSA / WFSA AD

24 TA.: FD WFSA FADC(AD) SDF FADC PMT FADC FADC bit MHz tov LSB.mV.. FADC FPGA(Field Programmable Gate Array) FADC bin bit MHz Σ o MHz ns EHECR ( ) FPGA Xilinx IIEs kbyte.µs.µs (. ) EHECR

25 ...:. FD.: Σ / HIT.µs TF FADC / NC(Non Conditional) TF NC PMT PMT PMT TF SDF x HIT xbit HIT xbit PMT HIT (Full Track ) CTD PMT HIT Partial Track CTD Partial Track NC NC CTD

26 TA CTD Final Trigger Full Track TF Partial Track NC.µs.µs SDF Final Trigger TF TF Final Trigger SDF Trigger PC(Mirror PC) Final Trigger HIT SDF Final Trigger PC TF HIT TF SDF TF SDF,TF.µs.µs.µs CTD.µs,.,.,.µs CTD Final Trigger GPS GPS ±ns ns(=mhz) CTD CTD TF SDF TF FPGA CTD SDF Σ SDF FPGA Memory Block Memory Block PMT (.µs ) Σ bit Byte HIT bit bit Memory Block

27 .. PMT kbyte TF kbyte FPGA VME ( SNLVTHA) VME VME (SBS model, bit) PC(Mirror PC) bit PCI nonblock DMA MByte/s Hz Hz(=MByte/s)

28 Signal Digitizer and Finder SDF. n SDF n.. ev EHECR. PMT (?? Θ) (?? θ) FD FD. PMT ns µs ns µs µs. P ψ ψ O β α P M Θ O M.: O FD M ψ α FD β FD Θ =π/ α =,β = α = arctan(tan / tan Θ),β = arctan(tan / tan Θ) Θ ψ ψ

29 ... SDF FADC SDF. PMT id fitting SDF Σ count entry micro second SDF Σ count.: SDF ( ) ( ).. Σ.. µv µv Σ (C Σ ) (N pe ) C Σ = eg PMTG AMP R L N pe (.) t V =. G PMT N pe (.) e. C G PMT PMT G AMP. R L PMT Ω t Σ ns V Σ V/ =.mv G PMT C Σ /N pe =. Σ....photo electron Utah.photo electron ( ) (WFSA) TA te t/τ τ t e t/τ τ (.) (.) τ [ns] τ p.e.

30 Signal Digitizer and Finder ns.. opeamp opeamp.. opeamp opeamp stdev/average.. arb.units timing constant [ns] nano second.: p.e. FADC δ ns,,,ns p.e.. ns δ p.e. (.). Pre AMP p.e. waveform mv ns.: p.e. p.e. PMT V PMT

31 .. input: ph.el equevarent charge sys./stat. error.. entry. input charge [eq. ph. el] output Σ count.: FADC ns p.e. FADC. p.e. p.e. p.e...v.v WFSA FADC WFSA.V.V WFSA SDF WFSA WFSA PMT ns WFSA..ns ns. WFSA.. WFSA ns ns WFSA.

32 Signal Digitizer and Finder input charge eq. p.e. Pre AMP input timing to.ns WFSA input charge eq. p.e. Pre AMP input timing to ns WFSA output voltage [mv] output voltage [mv] micro sec micro sec.:,wfsa( ).V FADC.V ns.ns ns ns max range [eq.p.e.] Pre AMP FADC width [ns].:. ns WFSA WFSA SDF WFSA / / WFSA

33 .....m PMT PMT ( ) Pre AMP WFSA.. ev,. ev,. ev,. ev [km] [km] [km] [km] [km] [km] [km] [km].:. ev,. ev,. ev,. ev tan, tan SDF WFSA SDF WFSA km

34 Signal Digitizer and Finder. FD..,,,.. ev FD km [km] [km] [km] [km] [km] [km] [km] [km].:. ( ev). ev FD...km.km / km ev ( )

35 .. saturated event triggrered event all event [km] number of event [km] impact parameter [km].: ev km FD () SDF WFSA SDF WFSA WFSA. TA SD FD. ψ β α t FD () R tc = OP ( PP OP cosψ = R cos(α ψ) cos ψ cos(β ψ) ) sin(β α) cos ψ cos(α ψ) cos(β ψ) (.) ψ Θ cos θ = cos ψ sin Θ (.) Θ FD Θ π/ ψ θ Θ=π/....

36 Signal Digitizer and Finder t t FD PMT / t. km ns ev km ns required time resolution [ns] core distance km km km required resolution [ns] core distance km km km incident angle [deg] incident angle [deg].: FD ( ) ( ) FADC MHz MHz ns. p.e./µs p.e./µs ns µs SDF FPGA

37 .. FPGA N N χ /(N ) N =.ms.ms ns µs PMT. PMT. core distance km elev degree degree degree degree acrossing time [ns] incident angle [deg].: PMT FD km o, o, o, o. o km PMT. PMT ns µs.µs,.µs,.µs,.µs

38 Signal Digitizer and Finder FPGA FPGA ns ns TW[ns] f(t) t = [ns] ns M, V TW f(t τ) dτ/ t M TW/ t (.) V TW/ t..,.,.,.µs ns..ms.,. / subhit subhit..µs subhit= / HIT TF.µs TF HIT. FADC / NC(Non Conditional) TF NC PMT

39 .. SDF. SDF SDF SDF PMT WFSA WFSA te t/ t ns WFSA PMT. te t/ / WFSA FADC FADC MHz DAC DAC MHz FPGA FPGA FADC FPGA.µs kbyte TF DAC FPGA VME CPLD(Xilinx XCXL). SDF ev... ±p.e./µs..... Hz Hz.

40 Signal Digitizer and Finder accidental trigger rate [Hz]. us window. us window. us window. us window all window camera..... threshould parameter.: PMT PMT.µs,.µs,.µs,.µs.. p.e./µs.... µs.µs.µs.. ev FD km sr

41 ...:. ev, km, ( ).µs without night sky background ns sampling basic data threshould. us moving average. us moving average. us moving average. us moving average threshould normalized count normalized count micro sec micro sec.:..,.,.,.µs.

42 Signal Digitizer and Finder [km] [km] [km] [km] [km] [km] [km] [km].:. ev,. ev,. ev,. ev SDF WFSA SDF WFSA km km

43 (.) TA Utah AGASA Utah.: SDF ( ) TF ( ). SDFTF PMT.

44 .: PMT ( ) ( ) Xeon Xeon. Xeon Xeon PMT FADC.µs FPGA FPGA FPGA WFSA. SDF µv, µv p.e...

45 .. Utah.: Xeon mv µs. Utah Utah Utah PMT. Xeon YAP( Am α ) Xeon YAP PMT Xeon PMT YAP YAP Xeon Xeon Xeon PMT PMT.: FD

46 PMT ±. p.e. =.±. YAP.:. PMT.. p.e. p.e./ns

47 .. Utah.: Utah Σ µs Σ PMT.. PMT Utah. FD. Σ. Σ. µs

48 .. average.,stdev.. urb.units... Σ counts.: Σ (n) (m) (σ) SDF C m = C n (.) σ = C n (.) (.) m =., σ=. C C = σ /m =. C =. ±. Σ p.e. SDF..

49 .. Utah.:.µs Σ /ns.:.µs Σ ns

50 PMT ( ) FD (Black Rock Mesa)

51 TA KEK SDF SDF

52 [] C.L.Bennet et al., ApJS,, () [] K. Griesen Phys. Rev. Lett., (). [] G.T. Zatsepin and V.A. Kuzmin, JETP. Lett., (). [] M.Takeda et al., Phys. Rev. Lett., () [] D.J. Bird et al., Phys. Rev. Lett., (). [] S. Yoshida th Omt. Cosmic Ray Conf. Pune, India,, Highlight talk [] R. D. Reece, Air Fluorescence Photon Yield In Cosmic Ray Showers Aug [] F. Kakimoto et al., Nucl. Instr. and Meth. A () [] T.Sanuki et.al., The Astrophys. J. () [] R.J.Protheroe., astroph/ [] T.Yamamoto., astroph/ [] GAISSER, Cosmic Rays and Particle Physics []

53 A A.:

54 B B. Pre AMP C (C) R (R) R (R) V O V I B.: Pre AMP I R = V I, R (B.) I R = V O V I, R (B.) I C = C ( V O V I ), (B.) I R = I R I C (B.) () () ( V O = R ) V I C R ( R V O V I ) = GV I τ( V I V O ) (B.) L LV (t) = G = R ( ), R (B.) τ = C R (B.) = Ṽ (s), L Ṽ (s) = V (t) V (t)e st dt

55 B.. SDF filter Ṽ O = G τs τs ṼI (B.) V I (t) =δ(t) V I (t) =Θ(t) V O (t) =δ(t) G e t τ τ ( ) V O (t) =Θ(t)(G ) e t τ (B.) (B.) B. SDF filter R C V I R Vm R V O C B.: SDF I R = V I V m R (B.) I R = V m V O R (B.) I R = V m R (B.) I C = C ( V m ) (B.) I C = C ( V O ) (B.) I R = I C (B.) I R = I R I R I C (B.) (),(),() V m = R C VO (B.)

56 B I R = V I R C VO R (B.) I R = V O R C VO R (B.) I R = C VO (B.) I C = C R C VO (B.) (),() () V I = { R R V O ( R C R C R ) R C R V O R C R C VO } (B.) DC V I = V O (B.) R R = V I = {V O (R C R C ) V } O R C R C VO (B.) (B.) = (V O A V O B VO ) (B.) A = R C /R C, (B.) B = R C R C (B.) Ṽ I Ṽ O = As B s (B.) A>B As B s = B (s α)(s β) (B.) A = B As B s = B (s /B) (B.) A<B As B s = B { (s σ) ω } (B.) α = A A B B, (B.) β = A A B B, (B.) σ = A B, (B.) ω = B A B (B.)

57 B.. SDF filter V I (t) = δ(t) V O (t) = e βt e αt B (α β) (A >B) (B.) = te t/b B (A = B) (B.) = e σt sin ωt B ω (A <B) (B.) V I (t) = Θ(t) V O (t) = αe βt βe αt α β (A >B) (B.) = e t/b t B e t/b (A = B) (B.) = e σt cos ωt σ ω e σt sin ωt (A <B) (B.)

58 C SDF

59 D[:] D[:] AM[:] A[:].V TMS TCK TDI TDO TDO TCK TMS DAT DAT DAT DAT DAT DAT DAT DAT AM D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT A A A A A A A A A IRQ[:] DAT DAT DAT DAT A A A A A A A A A[:] ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS A A A A A A A AM AM AM AM AM D D D D D D D D D D D D D D IRQ[:] DAT[:] /GATE TDI D[:] S /S S /S A[:] DAT[:] A[:] A A A A A A A A A A IRQ A A IRQ A A IRQ A A IRQ A A IRQ A A IRQ A A IRQ A dsb sysrst dsb lword writeb AM dtackb AM AM asb AM AM iackb iackin iackoutb iackb asb dtackb writeb dsb dsb A A A A A A A A D D D D D D D D D D D D A[:] GATEDIR /GATE LRESET A A ADRS[:] IRQ IRQ IRQ IRQ IRQ IRQ IRQ A A D[:] D[:] D[:] D[:] D D D D /IRQ A A D[:] DAT[:] AM[:] A[:] IRQ[:] D[:] A[:] AM lword.v iackin sysrst AM[:].V A[:].V dtack iackout A iackoutb IRQ[:] irq A[:] Vin STS S.V S.V SV HIT HIT# HIT HIT# HIT HIT# HIT HIT# HIT HIT# HIT HIT# HIT HIT# HIT HIT# HIT HIT# Vin.V.V.V C.V.V C * a a HIT b b HIT# c c a a HIT a b c.v b b HIT#.V a b c c c a b c a a HIT a b c b b HIT# a b c * C c c a a C a b c HIT S /S J a b c IC b b HIT# S /S HIT IC a b c c c S /S HIT HIT S S /S HIT S SIN HIT# D R D R a b c a a a b c b b SIN HIT DE DE c c.v *IC io HIT HIT /S /S R R NXABBAAAF NXABBAAAF NXABBAAAF a a.v.v HIT# HIT RE RE b b HIT SNMLVDD c c HIT HIT SNMLVDD C C C C a a C C C C C C C C C C HIT# HIT b b HIT c c R C a a HIT k HIT JE b b JD JF IC c c HIT a a HIT HIT LVDS.V b b D HIT.V c c DE HIT# a a R b b HIT# RE HIT# C c c SNMLVDD HIT# C *TestPin a a HIT# b b IC HIT# TP TP R TP e HIT# R S TP TP TP TP TP TP TP TP TP c c IC TP a a TP TP TP d f S D TP TP TP TP SIN d e f b b HIT# D SIN DE e c c d f HIT# DE e HIT# /S R d f a a HIT# /S R RE e b b d f RE d e f c c HIT# SNMLVDD S e /S HIT# a a SNMLVDD d f d S e /S f b b HIT# d S e /S f c c HIT# d S e /S f a a HIT# b b APA.DSA NXABBAAAF NXABBAAAF NXABBAAAF c c a a.v.v b b c c.v.v.v C a a.v b b C c c IC R a a R IC b b VCC IC S k c c S SOUT D R A Y a a SIN DE A Y SENSE VDD SW b b C /S R SENSE MR c c RE R SENSE RESET LRESET TPWW a a RESET SNLVCGDBVR b b k SNMLVDD c c TPSDGN.V a a b b IC c c a a VCC /S b b S/OUT A Y c c A Y a a b b C c c SNLVCGDBVR PCNP.DS SIN CLKIN VMECE_ VMEWR_ CCLK CCLK CCLK CCLK CCLK CCLK CCLK DAT[:].V INTCLK INTCLK R R R CCLK CCLK DIN RST SPIN SPOUT IRQ_ IRQCLR LRESET INIT_ DONE PGRM_ INIT_ DONE PGRM_ INIT_ DONE PGRM_ INIT_ DONE PGRM_ INIT_ DONE PGRM_ INIT_ DONE PGRM_ INIT_ DONE PGRM_ INIT_ DONE C R SIN PGRM_ INIT_ DONE PGRM_ SlaveCPLD SlaveCPLD INTCLK INTCLK SlaveCPLD SlaveCPLD SlaveCPLD SlaveCPLD SlaveCPLD SlaveCPLD INTCLK INTCLK INTCLK INTCLK INTCLK CLOCK SIN MHzCLK MasterCPLD_ MasterCPLD_ MasterCPLD_ MasterCPLD_.V.V.V.V ADRS[:] A B C R IC R R R R R R C R.V C S WCASS S WCASS RN CNJTTERJ RN CNJTTERJ S WCASS C J APA.DSA e e e e e e e e e J a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c A B A B A B A B SNMLVDD D DE R RE J APA.DS IC /GCK /GCK io /GTS /GTS /GTS /GTS io TCK TMS TDI io io io /GCK io io io io io io TDO io io /GSR JA a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c PCNP.DS JB C C C JC a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c PCNP.DS IC C DIR B B B B B B B B B B B B B B B B DIR IC IC DIR B B B B B B B B B B B B B B B B DIR OEB A A A A A A A A A A A A A A A A OEB SNLVTHADGGR OEB A A A A A A A A A A A A A A A A OEB SNLVTHADGGR C R R XCXLPQC C C Y A Y A Y A IC Y A Y A Y A SNLVCAPWR a a a a a a a a a d d d d d d d d d J a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c b b b b b b b b b u u u c c c c c c c c c f f f f f f f f f J a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c a b c A B A B A B k SNMLVDD D DE R RE

60 C SDF ch_sum ch_sum ch_sum ch_sum ch_sum ch_sum ch_sum ch_sum ch_sum Va Va Va DAAD[:] DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD BUSY HIT HIT HIT DAT[:] ADCA[:] DAAD[:] TMS_FPGA_ MasterCPLD_ MasterCPLD_ ADCA ADCA (MSB) ADCA ADCA ADCA ADCA ADCA ADCA ADCA ADCA ADCA ADCA (LSB) DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAAD DAT[:] DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS DAAD[:] ADCA[:] DAT[:] DAAD[:] ch_sum ADCA ADCA ADCA ADCA ADCA ADCA ADCA ADCA ADCA ADCA ADCA ADCA ADCA[:] land land land land land land land land land land land land land land land land ch_sum ch_sum ch_sum ch_sum ch_sum ch_sum DAC_SYNC DAC_SCLK DAC_DIN C C C Va Va C BLMPGSND Short ST(P) ST(N) Input span (VinaVinb),(Vpp) (MSB) (LSB).V Va ADACLK ADCA[:] ADCA[:] DAAD[:] DAACLK DAASLP A A A A A A A A A A A A A A A A OE OE OE OE Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Vd Va Vd HIFBAPA.DS ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch ch.v.v.v CLOCK TRIGGER VETO RESET ADACLK Vd C DAT[:] CCLK ADCA[:] IC OE A SNAHCTGDCKR DAAD[:] ADRS[:] ADRS[:] MasterCPLD_ (MSB) (LSB) Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave DAACLK DAASLP SWch SWch SWch SWch SWch SWch SWch SWch SWch SWch SWch SWch.V.Vd_FPGA Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave Slave HIT Slave Slave Slave SWch SWch SWch SWch DONE INIT_ PGRM_ DIN TCK_FPGA_.V.V.V R.k CLKIN VMEWR_ VMECE_ SPOUT IRQCLR IRQ_ SPIN DAC_SYNC DAC_SCLK DAC_DIN TDI_FPGA TDO_FPGA MHzCLK.V.V.V.V TDI_FPGA TDO_FPGA.V C.V INTCLK_FPGA_ RST Slave SIN SIN SIN DAT[:] SIN SIN CNJTTERJ CNJTTERJ SIN RN RN SOUT S/OUT HIT R BUSY LVDS MasterCPLD_ HIT RESET VETO Slave TRIGGER Va TP Test Pulse A TMS_FPGA_ TCK_FPGA_ TMS_FPGA_ TCK_FPGA_ TMS_FPGA_ TCK_FPGA_ J Y p L land land land land land land land land land land land land land land land land R k C SYNC SCLK DIN ADBRT IC Vout Vdd C IC ACTDL J HIFBAPA.DS B D C C D D E E E E G G G G G H H H H K K K K K M M N M M N N P P R R P R N P R N P R M N TMS M M M (DLL) D (DLL) A GCK,I C GCK,I B TCK A B A A C B C D E D B A C B A B C D E A A B C D A B C D E A B C D E D A B C B A A TDI C TDO B CCLK A C (DIN,D) B D E F G C D E F D E F G E F F F F F F J J J J L L L L L T T T T T P R T M N P R T T R P N T R P R T N M P R T T N M P N R P T R T R P P N N N M M M M L L L L K K K L K K J J J J H G H H G F H G (DLL) GCK,I GCK,I (DLL) DONE Program (INIT) R T T GNG R GNG L GNG L GNG K GNG K GNG K GNG K GNG J GNG J GNG J GNG J GNG H GNG H GNG H GNG H GNG G GNG G GNG G GNG G GNG F GNG F GNG B GNG B GNG A GNG A VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank F VCCO Bank F VCCO Bank E VCCO Bank F VCCO Bank F VCCO Bank E P P N N M M E E D D C C IC XCSEFTC C p O G V ICA A B A B EN VCC Y Y Y C FXOFL MHZ SNLVDSD IC R R R R R R R R R R R R R R R R R k R k R k R k R k R k R k R k R k R k R k R k R k R k R k Va C C R C C R k C R k R k R k C C R C C C C C IC AVDD OTR AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit DRVSS Bit(L) DRVDD CLK ADARS C C C C R.k C R R R C C Y Y Y A A A A G G R R C C *IC io.v.vd_fpga C C C C C C C C C C C C C C C C C C C C C C C RN CNJTTERJ ADAR CNJTTERJ RN J APA.DSA J APA.DSA J APA.DS C C p C C Va Z Z Z Z p VCC Y SNLVDSPW IC R C C R.k R R.k C C R Test Pulse B R R IC IC R R k R k ADAR ADAR R R.k C C C C R R k Va Va IC ADAR C CR MASD C C IC DB CLOCK DB DVDD DB DCOM DB NC DB AVDD DB ICOMP DB UTA DB UTB DB ACOM DB NC DB FS ADJ DB REF DB REFLO DB SLEEP ADAR ICB A B A B EN VCC Y Y C C C SNLVDSD DIR B B B B B B B B B B B B B B B B DIR IC OEB A A A A A A A A A A A A A A A A OEB SNLVTHADGGR C C C R C R k C C C R C R k R k R k

61 Va ch ch ch Va Va ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) DAT DAT DAT DAT DAT DAT DAT DAT ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADC_[:] ADC_[:] DAT[:] DAT[:] ADC_[:] ADC_[:] DAT[:] ADC_[:] R TP IC ch_sum R k AVDD OTR (MSB) AVSS Bit(M) SENSE Bit C C VREF Bit C REFCOM Bit R k CAPB Bit R k IC CAPT Bit R CML Bit R k C C VINA Bit ADAR VINB Bit CR C AVSS Bit C C AVDD Bit (LSB) DRVSS Bit(L) MASD Va DRVDD CLK R R R Va C C ADARS.V k k Va C R C C. L C C BLMPGSND Va Va C C IC Va C SWch IN IN Test Pulse A NO NO COM COM V Va COM COM Test Pulse_ch NO NO Test Pulse B IN IN SWch ADCLK ch Va R R ch_sum R k Va Test Pulse_ch Va Va Va Va.V Va ADCLK ADC_[:] ADC_[:] Va.V.Vd_FPGA DAT[:] CCLK ADC_[:] ADCLK ADCLK Vd Vd CLKIN VMEWR_ VMECE_ SPOUT IRQCLR IRQ_ SPIN SlaveCPLD Slave Slave Slave Slave TMS_FPGA_ ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) Slave Slave SlaveSlave_ SlaveSlave_ DONE DIN.V.V TCK_FPGA_.V SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ TDO_FPGA TDO_FPGA INIT_ PGRM_ ADC_[:] ADC_[:] INTCLK_FPGA_ DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT R TP R TP R.k C C C C TP land land C C C Input span Short (VinaVinb),(Vpp) ST(P) ST(N) TP R.k C C land land R k C R C R CR MASD C C BLMPGSND L Input span Short (VinaVinb),(Vpp) ST(P) ST(N) AVDD OTR (MSB) AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit (LSB) DRVSS Bit(L) DRVDD CLK C *IC io R C R R.k R.k RST DAT[:] CNJTTERJ ADRS[:] ADRS[:] RN p R R.k IC ADAR R k R k R. C C TP C C C C IC ADARS C ISLIV.V.Vd_FPGA C C C C C C C C C C C C C C C C R R R R.k V IC ADAR TP R.k TP C C C C C R IC OE A SNAHCTGDCKR RN CNJTTERJ J APA.DSA J APA.DSA p Y u R.k R.k R.k C R.k C C R k C R k C IC ADAR C C IC OE A SNAHCTGDCKR C B D C C D D E E E E G G G G G H H H H K K K K K M M N M M N N P P R R P R N P R N P R M N TMS M M M (DLL) D (DLL) A GCK,I C GCK,I B TCK A B A A C B C D E D B A C B A B C D E A A B C D A B C D E A B C D E D A B C B A A TDI C TDO B CCLK A C (DIN,D) B D E F G C D E F D E F G E F p Y F F F F F J J J J L L L L L T T T T T P R M N P R R P N T R P R T N M P R T T N M P N R P T R T R P P N N N M M M M L L L L K K K L K K J J J J H G H H G F H G T T T (DLL) GCK,I GCK,I (DLL) DONE Program (INIT) R T T GNG R GNG L GNG L GNG K GNG K GNG K GNG K GNG J GNG J GNG J GNG J GNG H GNG H GNG H GNG H GNG G GNG G GNG G GNG G GNG F GNG F GNG B GNG B GNG A GNG A VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank F VCCO Bank F VCCO Bank E VCCO Bank F VCCO Bank F VCCO Bank E P P N N M M E E D D C C IC XCSEFTC p u p C C C C C C C C C C C C C C C C C CNJTTERJ CNJTTERJ RN RN p

62 C SDF ch ch ch Va ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_[:] ADC_[:] ADC_[:] Va SWch Test Pulse A Va ch_sum Va Va Va Va Test Pulse_ch Test Pulse B SWch Va Va.V Va ADCLK ch Va Va Test Pulse_ch ch_sum Va Va Va Va.V Va ADCLK ADC_[:] ADC_[:] Va.V.Vd_FPGA DAT[:] DAT[:] DAT[:] CCLK ADC_[:] ADC_[:] ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) DAT DAT DAT DAT DAT DAT DAT DAT ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADC_[:] DAT[:] ADCLK ADCLK Vd Vd CLKIN VMEWR_ VMECE_ SPOUT IRQCLR IRQ_ SPIN SlaveCPLD Slave Slave Slave Slave TMS_FPGA_ Slave Slave SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ DONE DIN.V.V TCK_FPGA_.V SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ TDO_FPGA TDO_FPGA INIT_ ADC_[:] ADC_[:] INTCLK_FPGA_ DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT R TP C C land land C Input span Short (VinaVinb),(Vpp) ST(P) ST(N) IC AVDD OTR (MSB) AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit (LSB) DRVSS Bit(L) DRVDD CLK ADARS TP land land TP IC C C *IC io APA.DSA J APA.DSA RST DAT[:] C TP R k C IC TP C C ADAR C R C C IC OE A SNAHCTGDCKR J R.k p Y R R.K IC IN NO COM COM NO IN IN NO COM V COM NO IN R k R k C R C C C ADAR IC C C C C C C C C ISLIV IC OE A SNAHCTGDCKR B D C C D D E E E E G G G G G H H H H K K K K K M M N M M N N P P R R P R N P R N P R M N TMS M M M (DLL) D (DLL) A GCK,I C GCK,I B TCK A B A A C B C D E D B A C B A B C D E A A B C D A B C D E A B C D E D A B C B A A TDI C TDO B CCLK A C (DIN,D) B D E F G C D E F D E F G E F R CNJTTERJ ADRS[:] ADRS[:] RN V u Y F F F F F J J J J L L L L L T T T T T p u p R R N M R N M N R R N N N M M M M H G H H G H G P R M N P R R P N T P T P T T P P T T R P P L L L L K K K L K K J J J J F T T T (DLL) GCK,I GCK,I (DLL) DONE Program (INIT) R T T GNG R GNG L GNG L GNG K GNG K GNG K GNG K GNG J GNG J GNG J GNG J GNG H GNG H GNG H GNG H GNG G GNG G GNG G GNG G GNG F GNG F GNG B GNG B GNG A GNG A VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank F VCCO Bank F VCCO Bank E VCCO Bank F VCCO Bank F VCCO Bank E P P N N M M E E D D C C IC XCSEFTC IC R k R k R k C C R ADAR R k R k R. C.V.Vd_FPGA C C C C C C C C C C C C C C C C PGRM_ R TP R.k R.k R.k ADAR C R C C C R. C R C CR MASD C C C C C C C BLMPGSND L C C TP R R.k R.k R.K C R.K C C R R k R k C R k R k R TP C CR MASD C C C C BLMPGSND L Input span Short (VinaVinb),(Vpp) ST(P) ST(N) IC AVDD OTR (MSB) AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit (LSB) DRVSS Bit(L) DRVDD CLK ADARS C C C C C C C C C C C C C C C C C C R R C RN CNJTTERJ R R R.k R.k p CNJTTERJ CNJTTERJ RN RN p p

63 ch ch ch Va Va ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_[:] DAT[:] ADC_[:] ADC_[:] SWch Test Pulse A Va ch_sum Va Va Va Va Test Pulse_ch Test Pulse B SWch Va.V Va ADCLK ch Va Va Test Pulse_ch ch_sum Va Va Va.V Va ADCLK ADC_[:] ADC_[:] Va.V.Vd_FPGA DAT[:] DAT[:] DAT[:] CCLK ADC_[:] ADC_[:].V.Vd_FPGA ADCLK ADCLK Vd Vd CLKIN VMEWR_ VMECE_ SPOUT IRQCLR IRQ_ SPIN SlaveCPLD Slave Slave Slave Slave TMS_FPGA_ ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) Slave Slave SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ DONE DAT DAT DAT DAT DAT DAT DAT DAT DIN TCK_FPGA_.V.V.V SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ TDO_FPGA TDO_FPGA INIT_ ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADC_[:] ADC_[:] ADC_[:] INTCLK_FPGA_ DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT R TP C land land TP C C Input span Short (VinaVinb),(Vpp) ST(P) ST(N) C (MSB) (LSB) R C IC land land TP C TP CR MASD Input span Short (VinaVinb),(Vpp) ST(P) ST(N) C (MSB) (LSB) C *IC io RST DAT[:] u p R TP R.k R.K C C R k R. CR MASD C C R R.k R.K ADAR R k R k R k R. IC AVDD OTR AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit DRVSS Bit(L) DRVDD CLK ADARS R C B D C C D D E E E E G G G G G H H H H K K K K K M M N M M N N P P R R P R N P R N P R M N TMS M M M (DLL) D (DLL) A GCK,I C GCK,I B TCK A B A A C B C D E D B A C B A B C D E A A B C D A B C D E A B C D E D A B C B A A TDI C TDO B CCLK A C (DIN,D) B D E F G C D E F D E F G E F PGRM_ R R.k p F F F F F J J J J L L L L L T T T T T R R N M R N M N R R N N N M M M M H G H H G H G P R M N P R R P N T P T P T T P P T T R P P L L L L K K K L K K J J J J F T T T (DLL) GCK,I GCK,I (DLL) DONE Program (INIT) R T T GNG R GNG L GNG L GNG K GNG K GNG K GNG K GNG J GNG J GNG J GNG J GNG H GNG H GNG H GNG H GNG G GNG G GNG G GNG G GNG F GNG F GNG B GNG B GNG A GNG A VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank F VCCO Bank F VCCO Bank E VCCO Bank F VCCO Bank F VCCO Bank E P P N N M M E E D D C C IC XCSEFTC IC ADAR C IC IN NO COM COM NO IN IN NO COM V COM NO IN R k C C C C R k C IC ADAR ISLIV RN CNJTTERJ V R.k R.K C IC ADAR R R k R k C R k R k R C C C C TP C R C C C C Va C C BLMPGSND L IC AVDD OTR AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit DRVSS Bit(L) DRVDD CLK ADARS C C TP TP R.k R.K C R R k R k C C R C C C C R C C C C C C Va C C C BLMPGSND L C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C R C IC OE A SNAHCTGDCKR IC OE A SNAHCTGDCKR R J APA.DSA J APA.DSA R R R.k R.k CNJTTERJ ADRS[:] ADRS[:] RN p p Y u CNJTTERJ CNJTTERJ RN RN Y p p

64 C SDF ch ch ch Va Va ch_sum Va Va Va ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_[:] DAT[:] ADC_[:] ADC_[:] Va Va.V Va ADCLK ch Va Va Test Pulse_ch ch_sum Va Va Va.V Va ADCLK SWch Test Pulse A Va ADC_[:] ADC_[:] Va.V.Vd_FPGA DAT[:] DAT[:] DAT[:] CCLK ADC_[:] ADC_[:].V.Vd_FPGA ADCLK ADCLK Vd Vd CLKIN VMEWR_ VMECE_ SPOUT IRQCLR IRQ_ SPIN SlaveCPLD Slave Slave Slave Slave TMS_FPGA_ ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) Slave Slave SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ DONE DAT DAT DAT DAT DAT DAT DAT DAT TCK_FPGA_ DIN.V.V.V SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ TDO_FPGA TDO_FPGA INIT_ PGRM_ ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADC_[:] ADC_[:] ADC_[:] INTCLK_FPGA_ DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT R TP TP R.k R.k R.K C R.K C C IC C land land TP R k C C C C C C BLMPGSND L Input span Short (VinaVinb),(Vpp) ST(P) ST(N) (MSB) (LSB) R TP R.k C C land land TP R R k C R k R k C R C IC C C C C C C C BLMPGSND L Input span Short (VinaVinb),(Vpp) ST(P) ST(N) IC AVDD OTR (MSB) AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit (LSB) DRVSS Bit(L) DRVDD CLK ADARS C *IC io B D C C D D E E E E G G G G G H H H H K K K K K M M N M M N N P P R R P R N P R N P R M N TMS M M M (DLL) D (DLL) A GCK,I C GCK,I B TCK A B A A C B C D E D B A C B A B C D E A A B C D A B C D E A B C D E D A B C B A A TDI C TDO B CCLK A C (DIN,D) B D E F G C D E F D E F G E F J APA.DSA R R.k R.k RST DAT[:] F F F F F J J J J L L L L L T T T T T u P R M N P R R P N T R P R T N M P R T T N M P N R P T R T R P P N N N M M M M L L L L K K K L K K J J J J H G H H G F H G T T T (DLL) GCK,I GCK,I (DLL) DONE Program (INIT) R T T GNG R GNG L GNG L GNG K GNG K GNG K GNG K GNG J GNG J GNG J GNG J GNG H GNG H GNG H GNG H GNG G GNG G GNG G GNG G GNG F GNG F GNG B GNG B GNG A GNG A VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank F VCCO Bank F VCCO Bank E VCCO Bank F VCCO Bank F VCCO Bank E P P N N M M E E D D C C C IC XCSEFTC R R.k p p p R k R k C R C C C R.k R.K R k ADAR R C C CNJTTERJ CNJTTERJ RN RN ADAR R C R.K CR MASD p R C R. IC ADAR IC AVDD OTR AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit DRVSS Bit(L) DRVDD CLK ADARS C C TP C IC C Va C C IC IN IN NO NO COM COM V COM COM NO NO IN IN ISLIV R IC OE A SNAHCTGDCKR R R CNJTTERJ ADRS[:] ADRS[:] RN V Y R R k C R k Rk C C TP CR MASD C C R ADAR C C R k R k R. C TP C C C C C C Va Test Pulse_ch Test Pulse B SWch C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C R C IC OE A SNAHCTGDCKR RN CNJTTERJ J APA.DSA p u Y p

65 ch ch ch Va.V ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_[:] ADC_[:] SWch Test Pulse A Va ch_sum Va Va Va Va Test Pulse_ch Test Pulse B SWch Va Va ADCLK ch Va Va Test Pulse_ch ch_sum Va Va Va Va.V Va ADCLK ADC_[:] ADC_[:] Va.V.Vd_FPGA DAT[:] DAT[:] DAT[:] CCLK ADC_[:] ADC_[:].V.Vd_FPGA ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADC_[:] ADC_[:] DAT[:] ADCLK ADCLK Vd Vd CLKIN VMEWR_ VMECE_ SPOUT IRQCLR IRQ_ SPIN SlaveCPLD Slave Slave Slave Slave Slave Slave TMS_FPGA_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ DONE DAT DAT DAT DAT DAT DAT DAT DAT DIN TCK_FPGA_.V.V.V SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ TDO_FPGA TDO_FPGA INIT_ ADC_[:] ADC_[:] INTCLK_FPGA_ DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT R TP R.k R.K land land TP R k IC IN NO COM COM NO IN IN NO COM V COM NO IN R k R k C C C C BLMPGSND L Input span Short (VinaVinb),(Vpp) ST(P) ST(N) C C (MSB) (LSB) TP R.k R.K C R.K C land land R R k R k C R k R. C C Input span Short (VinaVinb),(Vpp) ST(P) ST(N) C C C (MSB) (LSB) ISLIV C *IC io C B D C C D D E E E E G G G G G H H H H K K K K K M M N M M N N P P R R P R N P R N P R M N TMS M M M (DLL) D (DLL) A GCK,I C GCK,I B TCK A B A A C B C D E D B A C B A B C D E A A B C D A B C D E A B C D E D A B C B A A TDI C TDO B CCLK A C (DIN,D) B D E F G C D E F D E F G E F APA.DSA J APA.DSA PGRM_ R RST DAT[:] V u CNJTTERJ ADRS[:] ADRS[:] RN F F F F F J J J J L L L L L T T T T T p R R N M R N M N R R N N N M M M M H G H H G H G P R M N P R R P N T P T P T T P P T T R P P L L L L K K K L K K J J J J F T T T (DLL) GCK,I GCK,I (DLL) DONE Program (INIT) R T T GNG R GNG L GNG L GNG K GNG K GNG K GNG K GNG J GNG J GNG J GNG J GNG H GNG H GNG H GNG H GNG G GNG G GNG G GNG G GNG F GNG F GNG B GNG B GNG A GNG A VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank F VCCO Bank F VCCO Bank E VCCO Bank F VCCO Bank F VCCO Bank E P P N N M M E E D D C C IC XCSEFTC R TP R.k R.K C C C C Va R R k C C R k C Rk R C C C R. IC TP ADAR C R C CR MASD C C C Va C C IC AVDD OTR AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit DRVSS Bit(L) DRVDD CLK ADARS C R R TP C C IC TP C R k R k C C C C TP C CR MASD C C C C BLMPGSND L C R C IC OE A SNAHCTGDCKR IC OE A SNAHCTGDCKR RN CNJTTERJ J R R R.k R R.k.k p p p Y Y p u p C ADAR R k R R C IC AVDD OTR AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit DRVSS Bit(L) DRVDD CLK ADARS C C C C C C C C C C C C C C C C R R IC ADAR R.k C C C C C C C C C C C C C C C C C C C CNJTTERJ CNJTTERJ RN RN C IC ADAR

66 C SDF ch ch ch Va Va Va.V ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ DAT[:] DAT[:] ADC_[:] ADC_[:] DAT[:] ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADC_[:] ADC_[:] ADC_[:] Va ch_sum Va Va Va ADCLK ch Va Test Pulse_ch ch_sum Va ADCLK SWch Test Pulse A Va ADC_[:] ADC_[:] Va.V.Vd_FPGA DAT[:] CCLK ADC_[:].V.Vd_FPGA ADCLK ADCLK Vd Vd CLKIN VMEWR_ VMECE_ SPOUT IRQCLR IRQ_ SPIN SlaveCPLD Slave Slave Slave Slave Slave Slave TMS_FPGA_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ DONE INIT_ PGRM_ DAT DAT DAT DAT DAT DAT DAT DAT DIN.V.V TCK_FPGA_.V R SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ TDO_FPGA TDO_FPGA ADC_[:] ADC_[:] INTCLK_FPGA_ DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT R TP TP R.k C IC land land TP R C C C TP TP land land TP R R C C *IC io (MSB) (LSB) R.k RST DAT[:] u IC ADAR C C C C Va R k C R. C B D C C D D E E E E G G G G G H H H H K K K K K M M N M M N N P P R R P R N P R N P R M N TMS M M M (DLL) D (DLL) A GCK,I C GCK,I B TCK A B A A C B C D E D B A C B A B C D E A A B C D A B C D E A B C D E D A B C B A A TDI C TDO B CCLK A C (DIN,D) B D E F G C D E F D E F G E F R.k F F F F F J J J J L L L L L T T T T T P R T M N P R T T R P N T R P R T N M P R T T N M P N R P T R T R P P N N N M M M M L L L L K K K L K K J J J J H G H H G F H G (DLL) GCK,I GCK,I (DLL) DONE Program (INIT) R T T GNG R GNG L GNG L GNG K GNG K GNG K GNG K GNG J GNG J GNG J GNG J GNG H GNG H GNG H GNG H GNG G GNG G GNG G GNG G GNG F GNG F GNG B GNG B GNG A GNG A VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank F VCCO Bank F VCCO Bank E VCCO Bank F VCCO Bank F VCCO Bank E P P N N M M E E D D C C C IC OE A SNAHCTGDCKR IC XCSEFTC p Y p ADAR R k R k R C CR MASD C Va C C R R.K IC Va R k R k R k R k C C TP Va C BLMPGSND IN IN NO NO COM COM V COM COM NO NO IN IN ISLIV R R J APA.DSA J V p R R.k R.K C R.K R k R k C C R. TP R R.k ADAR C C R C C C R C RN CNJTTERJ u p C C R k R k C C C C C C BLMPGSND L Input span Short (VinaVinb),(Vpp) ST(P) ST(N) IC AVDD OTR (MSB) AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit (LSB) DRVSS Bit(L) DRVDD CLK ADARS C C R R.k R.K C C R k C IC ADAR C Va CR MASD C C C Input span Short (VinaVinb),(Vpp) ST(P) ST(N) IC AVDD OTR (MSB) AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit (LSB) DRVSS Bit(L) DRVDD CLK ADARS.V L C C Va C IC C C Va Test Pulse_ch Test Pulse B SWch C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C IC OE A SNAHCTGDCKR R R R APA.DSA.k CNJTTERJ ADRS[:] ADRS[:] RN p p Y CNJTTERJ CNJTTERJ RN RN

67 ch ch ch Va Va Va Va Va ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADC_[:] ADC_[:] DAT[:] ADC_[:] ADC_[:] Va SWch Test Pulse A Va ch_sum Va Va Test Pulse_ch Test Pulse B SWch.V Va ch Va Test Pulse_ch ch_sum Va Va.V Va ADCLK ADC_[:] ADC_[:] Va.V.Vd_FPGA DAT[:] DAT[:] DAT[:] CCLK ADC_[:] ADC_[:].V.Vd_FPGA ADCLK ADCLK Vd Vd CLKIN VMEWR_ VMECE_ SPOUT IRQCLR IRQ_ SPIN SlaveCPLD Slave Slave Slave Slave Slave Slave TMS_FPGA_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ DONE INIT_ PGRM_ DAT DAT DAT DAT DAT DAT DAT DAT DIN.V.V TCK_FPGA_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ TDO_FPGA TDO_FPGA ADC_[:] ADC_[:] INTCLK_FPGA_ DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT R TP TP C R.K C land land TP land land TP R C C *IC io B D C C D D E E E E G G G G G H H H H K K K K K M M N M M N N P P R R P R N P R N P R M N TMS M M M (DLL) D (DLL) A GCK,I C GCK,I B TCK A B A A C B C D E D B A C B A B C D E A A B C D A B C D E A B C D E D A B C B A A TDI C TDO B CCLK A C (DIN,D) B D E F G C D E F D E F G E F RST DAT[:] F F F F F J J J J L L L L L T T T T T P R T M N P R T T R P N T R P R T N M P R T T N M P N R P T R T R P P N N N M M M M L L L L K K K L K K J J J J H G H H G F H G (DLL) GCK,I GCK,I (DLL) DONE Program (INIT) R T T GNG R GNG L GNG L GNG K GNG K GNG K GNG K GNG J GNG J GNG J GNG J GNG H GNG H GNG H GNG H GNG G GNG G GNG G GNG G GNG F GNG F GNG B GNG B GNG A GNG A VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank F VCCO Bank F VCCO Bank E VCCO Bank F VCCO Bank F VCCO Bank E P P N N M M E E D D C C IC XCSEFTC p C R R k IC IN NO COM COM NO IN C IN NO COM V COM NO IN R k C R C C C R. IC C C Va C C C C TP R.k R.k R.K C R.K R C C R. IC ADAR R C C C C ISLIV R V p p CNJTTERJ ADRS[:] RN ADRS[:] u u ADAR TP R k R k R k C IC OE A SNAHCTGDCKR Y p R R.k R.K R k C R k R k R k C C TP C Va R C C C C R C C IC ADAR C Va R k R k C C CR MASD C C BLMPGSND L C C R C IC OE A SNAHCTGDCKR R R R J APA.DSA.V R.k J APA.DSA R.k R.k CNJTTERJ CNJTTERJ RN RN p Y R.k C IC ADAR CR MASD C BLMPGSND L Input span Short (VinaVinb),(Vpp) ST(P) ST(N) IC AVDD OTR (MSB) ADC_ AVSS Bit(M) ADC_ SENSE Bit ADC_ VREF Bit ADC_ REFCOM Bit ADC_ CAPB Bit ADC_ CAPT Bit ADC_ CML Bit ADC_ VINA Bit ADC_ VINB Bit ADC_ AVSS Bit ADC_ AVDD Bit (LSB) ADC_ DRVSS Bit(L) DRVDD CLK ADCLK ADARS C C R R k C C TP C C C C Input span Short (VinaVinb),(Vpp) ST(P) ST(N) IC AVDD OTR (MSB) AVSS Bit(M) SENSE Bit VREF Bit REFCOM Bit CAPB Bit CAPT Bit CML Bit VINA Bit VINB Bit AVSS Bit AVDD Bit (LSB) DRVSS Bit(L) DRVDD CLK ADARS C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C R C RN CNJTTERJ p

68 C SDF ch Va Va Va Input span Va Short (VinaVinb),(Vpp) Input span Va Short ST(P) (VinaVinb),(Vpp) land C C ST(P) land C C C ST(N) land C land ST(N) C C C C TP TP IC TP R ch_sum AVDD OTR TP IC (MSB) R R k ADC_ R AVSS Bit(M) ch_sum AVDD OTR ADC_ (MSB) ADC_ SENSE Bit R k AVSS Bit(M) ADC_ ADC_ VREF Bit TP R.K C C TP SENSE Bit C ADC_ ADC_ REFCOM Bit C ADC_ C C VREF Bit ADC_ IC R k CAPB Bit REFCOM Bit ADC_ R.k ADC_ R k IC CAPT Bit ADC_ IC R k CAPB Bit R ADC_ CML Bit ch R k ADC_ IC CAPT Bit R k ADC_ VINA Bit R ADAR CML Bit C C ADC_ ch R k ADC_ ADAR VINB Bit ADC_ ADAR C C VINA Bit ADC_ CR AVSS Bit R.k ADC_ ADAR VINB Bit C CR ADC_ C C AVDD Bit (LSB) ADC_ ADC_ DRVSS Bit(L) R C AVSS Bit MASD (LSB) ADC_ ADCLK DRVDD CLK C C AVDD Bit.K C MASD DRVSS Bit(L) Va ADCLK R R R C C ADARS.V C DRVDD CLK Va C Va C C R C R R R C.V k ADARS k Va C Va C R k k Va C L C. C C R BLMPGSND L. C C BLMPGSND Va Va Va Test Pulse_ch C C C IC Va C C SWch IN IN Test Pulse A NO NO COM COM V Va COM COM Test Pulse_ch NO NO Test Pulse B IN IN SWch ch Va ADC_[:] ADC_[:] ADC_[:] ADC_[:] Va.V.Vd_FPGA DAT[:] DAT[:] DAT[:] CCLK ADC_[:] ADC_[:].V.Vd_FPGA ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (MSB) ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ ADC_ (LSB) ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADRS ADC_[:] ADC_[:] DAT[:] ADCLK ADCLK Vd Vd CLKIN VMEWR_ VMECE_ SPOUT IRQCLR IRQ_ SPIN SlaveCPLD Slave Slave Slave Slave Slave Slave TMS_FPGA_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ SlaveSlave_ DONE DAT DAT DAT DAT DAT DAT DAT DAT DIN TCK_FPGA_.V.V.V TDO_FPGA TDO_FPGA INIT_ ADC_[:] ADC_[:] INTCLK_FPGA_ DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT R TP TP R.K C *IC io R C (MSB) (LSB) J APA.DSA J RST DAT[:] p p R R.k R.K C C IC OE A SNAHCTGDCKR RN CNJTTERJ R R PGRM_ R p Y u R.k C ISLIV C C C C C C C C C C C C C C C C R C B D C C D D E E E E G G G G G H H H H K K K K K M M N M M N N P P R R P R N P R N P R M N TMS M M M (DLL) D (DLL) A GCK,I C GCK,I B TCK A B A A C B C D E D B A C B A B C D E A A B C D A B C D E A B C D E D A B C B A A TDI C TDO B CCLK A C (DIN,D) B D E F G C D E F D E F G E F R R.k.k CNJTTERJ ADRS[:] ADRS[:] RN F F F F F J J J J L L L L L T T T T T p R P R N M P R N M P N R P R R P P N N N M M M M K K K K K H G H H G H G P R M N P R R P N T T T T T T L L L L L J J J J F T T T (DLL) GCK,I GCK,I (DLL) DONE Program (INIT) R T T GNG R GNG L GNG L GNG K GNG K GNG K GNG K GNG J GNG J GNG J GNG J GNG H GNG H GNG H GNG H GNG G GNG G GNG G GNG G GNG F GNG F GNG B GNG B GNG A GNG A VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank M VCCO Bank L VCCO Bank L VCCO Bank K VCCO Bank J VCCO Bank J VCCO Bank H VCCO Bank H VCCO Bank G VCCO Bank F VCCO Bank F VCCO Bank E VCCO Bank F VCCO Bank F VCCO Bank E P P N N M M E E D D C C IC OE A SNAHCTGDCKR IC XCSEFTC APA.DSA R.k V p p Y C C C C C C C C C C C C C C C C CNJTTERJ CNJTTERJ RN RN u

69 Vin SI L Vd TP L TP Va.V SSFRAN SI SSFRAN C uf C uf C uf C uf C C B CB PSG CG BNX L B CB PSG CG BNX Vd C uf C uf C uf C uf C L B CB PSG CG BNX C uf C uf C TP Va C uf C C uf INTCLK INTCLK INTCLK INTCLK A A A A Y Y Y Y.V C INTCLK_FPGA_ INTCLK_FPGA_ L B CB.V INTCLK_FPGA_ INTCLK_FPGA_.V.V R.Vd_FPGA.Vd_FPGA.Vd_FPGA INTCLK INTCLK INTCLK INTCLK.V.V.V.V INTCLK_FPGA_ INTCLK_FPGA_ INTCLK_FPGA_ INTCLK_FPGA_ J.V.Vd_FPGA.Vd_FPGA INTCLK INTCLK_FPGA_ C IC SHDN OUT SEN TP IC A B A B Y Y SNLVDSD C IC A Y A A Y Y A A Y Y A Y SNLVAD C uf R R IN C uf LTES. C C C uf C IC A B A B Y Y SNLVDSD STN R IC A B A B Y Y SNLVDSD.V R k TP C uf A A A A Y Y Y Y.V R k C G G Z Z Z Z VCC IC SHDN OUT SEN IC SNLVDSPW C IN C C LTES. R C R R IC SHDN OUT SEN IN LTES. IC A A A A Y Y Y Y G G Z Z Z Z VCC SNLVDSPW G G Z Z Z Z VCC IC C TP SNLVDSPW R SSFRAN PSG CG SI C C SSFRAN BNX uf.v R.k C C IC A Y A A Y Y A A Y Y A Y SNLVAD.V R k C uf C uf TP C uf C C R R C C C uf TP C R J FA C TP B CB PSG CG BNX.V C R R IC A B A B Y Y SNLVDSD SI L B CB PSG CG BNX C IC SHDN OUT SEN IC SHDN OUT SEN C uf IN LTES. IN C LTES. R C uf IC A B A B Y Y SNLVDSD.V R k C C C TP R