13 Verilog HDL 16 CPU CPU IP
16 1023 2 reg[ msb: lsb] [ ]; reg [15:0] MEM [0:1023]; //16 1024 16 1 16 2 FF
1 address 8 64 `resetall `timescale 1ns/10ps module mem8(address, readdata,writedata, write, read); parameter address_size = 6, mem_size = 64; input [address_size-1:0] address; input [7:0] writedata; output [7:0] readdata; input write, read; writedata readdata reg [7:0] mem [0: mem_size-1]; reg [7:0] readdata; read write always @( read or write or address) begin if ( write == 1'b1 ) mem[ address ] <= writedata; end else readdata <= mem[address]; endmodule
2 inout address 3 8 memout writedata rwdata `resetall `timescale 1ns/10ps module mem8b( address, rwdata, read, write); parameter address_size = 3, mem_size = 8; input [address_size-1:0] address; inout [2: 0] rwdata; input read, write; reg [2:0] mem [ 0: mem_size-1]; reg [2:0] memout; assign rwdata = (read)? memout : 8'bz; always @( read or write or address ) begin if ( write ) mem[address] = rwdata; memout = mem[address]; read write end endmodule Tr
2 FPGA,GA FF 2 16 RAM FPGA A3 GND IP
SRAM ADDR stable stable stable t AA READ t Ac t OZ t OZ DOUT valid valid thd WRITE DIN tst stable SRAM
16 CPU PLD CPU CPU 12 12
16 CPU 1 3 16 323 2 1 ALU: I/O I/O /
CPU SRAM RAM) DRAM( RAM) MRAM,FeRAM,OUM,RRAM SRAM: RS DRAM SRAM Spartan II
16 CPU 1) Add, Sub, Xor, AND,ShiftLeft, ShitRight OP[11:0] 12 (OP[11:0]) 2) LDA, STA, LDI (12) LDI 3) / JPZ JMP 4) / JL, RET (12) LDI 5) Halt OP Code OP Code ALU 0 PC PC ALU ALU ALU 12 16 Add Sub Xor AND SRL SRR LDA LDI STA JMP JPZ JL RET NOP HALT 1000 1001 1011 1010 1100 1101 0001 0011 0010 0100 0101 0110 0111 0000 1111 A+B A B A B A B A<< OP[11:0] A>> OP[11:0] B B A Acc Acc (OP[11:0]), PC PC+1 Acc Acc (OP[11:0]), PC PC+1 Acc Acc XOR (OP[11:0]), PC PC+1 Acc Acc AND (OP[11:0]),PC PC+1 Acc Acc<< OP[11:0], PC PC+1 Acc Acc>> OP[11:0], PC PC+1 Acc (OP[11:0]), PC PC+1 Acc OP[11:0], PC PC+1 (OP[11:0]) Acc, PC PC+1 PC OP[11:0] PC OP[11:0] if Zero/ PC PC+1 if not Zero PC OP[11:0], BAR PC+1) PC BAR PC PC+1 All outputs are 0
LDI OP[15:12] LDI OP[15:12] OP[11:0] (12) OP[11:0] (12) 12 K 16 8 0) PC 1) 2) 3) 4) 5) LDA,ALU 6) 7) ACC
16bit CPU Architecture ver1.10 2002/11/09 LD-Bar Reset LD-PC Inc-PC Reset Sel-PC BAR pc_out PC pc_dat oprand(ir_out[11:0]) 12 16 Sign Extend IR ir_out Sel-Madd LD-IR Reset Mem-add Memory 000 EFFF Memory Mapped I/O F000 FFF bar_out Op(IR[15:12]) ext_ir 1 0 mem_dat mem_buf Mem-data LD-AC Reset ACC acc_out b_out Sel-IM Zero Reset Clock BAR, PC, IR, ACC have output signal for LED Op(IR[15:12]) CONT opcode ALU alu_out Halt Sel-Madd En-MOdat LD-PC Inc-PC LD-Bar LD-AC LD-IR Sel-PC Mem-RD Mem-WD Sel-IM Zero Mem-RD Mem-WD En-MOdat alu_buf Buf Clock Mem-Read Mem-Write
8 LDA 0) 1 PC 8 1) 2) IR IR 3) 0) 1 4) 2 1) 2) 3) IR PC 5) ACC 6) ALU ACC 7) ACC 4) 2 0) 1 5) 1) 6) 7)
0) 1 Memory 000 EFFF BAR Mem-add PC 100 Sign Extend IR #100 12 16 Mem-data Op ext_ir 1 0 mem_dat mem_buf #200 Clock ACC acc_out b_out ALU alu_out alu_buf PC #100 LDA #1200 #200 #5AA5
1) Memory 000 EFFF BAR Mem-add PC 100 Sign Extend IR 1200 #100 12 16 Mem-data Op ext_ir 1 0 mem_dat mem_buf #200 Clock ACC acc_out b_out ALU alu_out alu_buf
2) IR) Memory 000 EFFF BAR Mem-add PC 100 Sign Extend IR 1200 #100 12 16 1200 Mem-data Op ext_ir 1 0 mem_dat mem_buf #200 Clock ACC acc_out b_out ALU alu_out alu_buf
3) Memory 000 EFFF BAR Mem-add PC 100 Sign Extend IR 1200 #100 12 16 1200 Mem-data Op ext_ir 1 0 mem_dat mem_buf #200 Clock ACC acc_out b_out ALU alu_out alu_buf
4) 2 IR[11 0 Memory 000 EFFF BAR Mem-add PC 100 101 Sign Extend IR 1200 #100 12 16 1200 Mem-data Op ext_ir 1 0 mem_dat mem_buf #200 Clock ACC acc_out b_out ALU alu_out alu_buf PC HALT
5) Memory 000 EFFF BAR Mem-add PC 101 Sign Extend IR 1200 #100 12 16 1200 Mem-data Op ext_ir 1 0 mem_dat mem_buf 5AA5 #200 Clock ACC acc_out b_out ALU alu_out alu_buf
6) Memory 000 EFFF BAR Mem-add PC 101 Sign Extend IR 1200 #100 12 16 1200 Mem-data Op ext_ir 1 0 mem_dat mem_buf 5AA5 #200 Clock ACC acc_out b_out ALU alu_out alu_buf ALU
7) Memory 000 EFFF BAR Mem-add PC 101 Sign Extend IR 1200 #100 12 16 1200 Mem-data Op ext_ir 1 0 mem_dat mem_buf 5AA5 #200 Clock 5AA5 ACC acc_out b_out ALU alu_out alu_buf 8 LDA
0) 1( Memory 000 EFFF BAR Mem-add PC 101 12 16 Sign Extend 1200 IR 1200 #100 #101 Mem-data Op ext_ir 1 0 mem_dat mem_buf 5AA5 #200 Clock 5AA5 ACC acc_out b_out ALU alu_out alu_buf PC (#101)
1 ALU 2
3 4
#000 LDI 0 0 #001 STA #20 #20(Total) #002 STA #21 #21( i) #003 LDI 1 1 0 50 #004 STA #22 #22 1 #005 LDI 50 50 #006 STA #23 #23( 50 #007 JL #010 #10 #008 STA #F00 total = 0; i= 1; #009 HALT end = 50; a= sum(); output a; int sum(){ total = 0; for (int j=0; j<=end; j= j+i) total = total + j; return total; } #010 LDA #21 i ( #011 ADD #22 i+1 #012 STA #21 i #013 ADD #20 i+w #014 STA #20 w #015 LDA #21 i #016 SUB #23 i-50 #017 JPZ #19 Zero#19 #018 JMP #010 #019 LDA #20 Total #01B RET #020 DC Total DC #021 DC i #022 DC : #023 DC 50
Reset 0 0 0
IP FPGA FPGAIP FPGA IP
CPU VerilogHDL Spartan II 3 7 16 I/O#F00 - ALU, 7 16 TOP 8 - / PC 000 1 7 LED5 LED RUN
SRAM IP data address clk Xillinx IP sram16x256). sram / write read sram sram16x256 din addr clk we dout `timescale 1ns/10ps module sram( data, address, read, write, clk ); inout [15:0] data; input [11:0] address; input read; input write; input clk; wire [15:0] out; wire [7:0] addr256; assign addr256=address[7:0]; sram16x256 s1(.addr(addr256),.clk(clk),.din(data),.dout(out),.we(write ); bufif1 DATA_BUF00(data[0],out[0],read); bufif1 DATA_BUF01(data[1],out[1],read); bufif1 DATA_BUF02(data[2],out[2],read) bufif1 DATA_BUF03(data[3],out[3],read); bufif1 DATA_BUF04(data[4],out[4],read); bufif1 DATA_BUF05(data[5],out[5],read); bufif1 DATA_BUF06(data[6],out[6],read); bufif1 DATA_BUF07(data[7],out[7],read); bufif1 DATA_BUF08(data[8],out[8],read); bufif1 DATA_BUF09(data[9],out[9],read); bufif1 DATA_BUF10(data[10],out[10],read); bufif1 DATA_BUF11(data[11],out[11],read); bufif1 DATA_BUF12(data[12],out[12],read); bufif1 DATA_BUF13(data[13],out[13],read); bufif1 DATA_BUF14(data[14],out[14],read); bufif1 DATA_BUF15(data[15],out[15],read); endmodule IP
/ RAM FPGA.coe.coe.coe MEMORY_INITIALIZATION_RADIX=16; MEMORY_INITIALIZATION_VECTOR=123,456,..,..,AAA 10.coe IP
IP 1/6
IP 2/6 $XLINX Verilog
IP 3/6 Basic Elements RAM
IP 4/6 Memory Elements Single Port Block Memory
IP 5/6 1 Single Port Block Memory 2
IP 6/6.coe
VerilogHDL 1/2 IP ( Verilog Style Program Setup..
VerilogHDL 2/2 translate_on