LSI LSI 2
P=CV 2 F 3
4
5
EDA Electric Design Automation) LSI CAD Computer Aided Design) Verilog Verify Logic VHDL VHSIC Description Language) SystemC C SFL Structured Functional description Language) NTT 6
LSI 7
(FPGA: Field Programmable Gate Array) 8
1. 2. 9
1. 2. 3. 10
FSM CPU VGA NTSC SEG LED 11
12
module comb (b, a, f ); input b; input a; output f; assign f = a&b; endmodule library ieee; use ieee.std_logic_1164.all; entity comb is port( f: out std_logic; b: in std_logic; a: in std_logic); end comb; architecture RTL of comb is begin f <= a and b; end RTL; module comb { input a,b; output f; f=a&b; } 13
module regi (m_clock, a, f ); input m_clock; reg r; input a; output f; assign f = r; always @(posedge m_clock ) begin r <= a; end endmodule library ieee; use ieee.std_logic_1164.all; entity regi is port(m_clock: in std_logic; f: out std_logic; a: in std_logic); end regi; architecture RTL of regi is signal r: std_logic; begin f <= r; p_0: process(m_clock) begin if m_clock'event and m_clock='1' then r <= a; end if; end process; end RTL; module regi { input a; output f; reg r; par { r := a; f = r; } } 14
parameter _state_sg st0 = 0; parameter _state_sg st1 = 1; parameter _state_sg st2 = 2; assign _net_2 = ((_stage_sg_state_reg)==(_state_sg st2))&_stage_sg; assign _net_1 = ((_stage_sg_state_reg)==(_state_sg st1))&_stage_sg; assign _net_0 = ((_stage_sg_state_reg)==(_state_sg st0))&_stage_sg; always @(posedge m_clock or posedge p_reset) begin if (p_reset) _stage_sg_state_reg <= _state_sg st0; else if (_net_2) _stage_sg_state_reg <= _state_sg st0; else if (_net_1) _stage_sg_state_reg <= _state_sg st2; else if (_net_0) _stage_sg_state_reg <= _state_sg st1; end constant v_state_sg_v_st0: std_logic_vector(1 downto 0) := 0; constant v_state_sg_v_st1: std_logic_vector(1 downto 0) := 1; constant v_state_sg_v_st2: std_logic_vector(1 downto 0) := 2; v_net_5 <= (v_net_4) and v_stage_sg; v_net_4 <= '1' when ((v_stage_sg_state_reg) = (v_state_sg_v_st2)) else '0' ; v_net_3 <= (v_net_2) and v_stage_sg; v_net_2 <= '1' when ((v_stage_sg_state_reg) = (v_state_sg_v_st1)) else '0' ; v_net_1 <= (v_net_0) and v_stage_sg; v_net_0 <= '1' when ((v_stage_sg_state_reg) = (v_state_sg_v_st0)) else '0' ; p_0: process(m_clock) begin if m_clock'event and m_clock='1' then if p_reset='1' then v_stage_sg_state_reg <= v_state_sg_v_st0; elsif (v_net_5)='1' then v_stage_sg_state_reg <= v_state_sg_v_st0; elsif (v_net_3)='1' then v_stage_sg_state_reg <= v_state_sg_v_st2; elsif (v_net_1)='1' then v_stage_sg_state_reg <= v_state_sg_v_st1; else v_stage_sg_state_reg <= "00"; end if; end if; end process; module sttest { stage_name sg { task t1(); } stage sg { state_name st0,st1,st2; first_state st0; state st0 goto st1; state st1 goto st2; state st2 goto st0; } } 15
16
CPU CPU 17
AFPGA 18
FPGA 19
LSI LSI 20
FF) flip flop, register, latch, memory 21
LSI LSI 22
1 02 23
24
a,b,c a b f 0 0 0 f 0 1 0 1 0 0 (1) f = a & b (2) f = a & (b c) (3) f = a (^b & c) 1 (1) 1 1 25
a b c f Don t Care 0 0 0 0 0 0 1 1 0 1 0 0 * 1 1 1 1 0 0 1 1 0 1 0 1 1 0 0 f(2) f(4) f(5) f=f(2) f(4) f(5) 26
A&B = B&A A B = B A A (B&C) = (A B)&(A C) A&(B C) = (A&B) (A&C) (A&B)&C = A&(B&C) (A B) C = A (B C) 27
A&(A B) = A A (A&B) = A f(&,,a,b,c, ) = f(,&,a,b,c, ) A&B C = (A B) & C 28
29
A,B C S,T,U S U S,T,U A B C : S T U 30
LSI LSI 31
D Q 32
33
S1, S0 N1, N0 Det 34
: Finite State Machine 35
B,Y,R Wb,Wr P Don t care() 36
37
A B C A A 38
LSI LSI 39
40
4 4+4 char 8 char a,b 100 c=a+b #include <stdio.h> int main () { char a,b,c; a=100; b=100; c=a+b; printf("a=%d, b=%d, c=%d n",a,b,c); } 41
K V=diK (i-f) f 10 ABC 42
A BCD E F A F D 43
44
floating point number) X fixed point number) 45
IEEE sign) S (exponent)e (Mantissa)M 46
S 1.xxxxxx 2 K xxxxxx M K E KE 47
1 01111111 000 0000 0000 0000 0000 0000 P.124 4.5 (1),(2) 48
LSI LSI 49
50
1. 2. 51
L L L 52
1. 2. 3. 53
54
P129 55
R R O R Q Q Q seladdh seladdm seladdl A B c Oc selcin0 selcinc woc woh O wom O wol RQ O 56
seladdl=1 selcin0=1 woc=1 wol=1 seladdm=1 selcinc=1 woc=1 wom=1 seladdh=1 selcinc=1 woc=1 woh=1 57
58
selaint selainr R R Ot wot O R Q Q Q seladdh seladdm seladdl 6 A B c selbin6 selbinq Oc selcin0 selcinc O O woh wom RQ O woc wol 59
AC 60
61 R R R Q Q Q Oc Ot O O O AC selqin0 selqinkey selrin0 selrinkey seladdh seladdm seladdl seloin0 seloinadd seloinkey A B selaint selainr selbin6 selbinq Kin 6 c selcin0 selcinc
62 R R R Q Q Q Oc Ot O O O AC selqin0 selqinkey selrin0 selrinkey seladdh seladdm seladdl seloin0 seloinadd seloinkey A B selaint selainr selbin6 selbinq Kin 6 c selcin0 selcinc Oh O O
63
64
instruct setrh Rh := key; /* */ instruct setrm Rm := key; /* instruct setrl Rl := key; */ instruct setqh Qh := key; module add12 { instruct setqm Qm := key; input key<4>; instruct setql Ql := key; instrin setrh, setrm, setrl, setqh, setqm, setql; instrin doadd; output outh<4>, outm<4>, outl<4>; reg Rh<4>, Rm<4>, Rl<4>, Qh<4>, Qm<4>, Ql<4>, Oc; reg Oh<4>, Om<4>, Ol<4>; instrself seladdh, seladdm, seladdl, selcin0, selcinc; instrself woc, woh, w0m, wol, exec_add; sel addina<4>, addinb<4>, addinc, addout<5>; instruct seladdh par { addina = Rh; addinb = Qh; } instruct seladdm par { addina = Rm; addinb = Qm; } instruct seladdl par { addina = Rl; addinb = Ql; } instruct selcin0 addinc = 0b0; instruct selcinc addinc = Oc; instruct woc Oc := addout<4>; instruct woh Oh := addout<3:0>; instruct wom Om := addout<3:0>; instruct wol Ol := addout<3:0>; instruct exec_add addout = addina + addinb + addinc; stage_name exec {task t();} par { outh = Oh; outm = Om; outl = Ol; } instruct doadd generate exec.t(); } stage exec { state_name invoke_wait, calcl, calcm, calch; first_state invoke_wait; state invoke_wait goto calcl; state calcl par { seladdl(); selcin0(); woc(); wol(); exec_add(); goto calcm;} state calcm par { seladdm(); selcinc(); woc(); wom(); exec_add(); goto calch;} state calch par { seladdh(); selcinc(); woc(); woh(); exec_add(); goto invoke_wait; finish;} } 65
SFL SFL : calculator : key<4> : outl<4>, outm<4>, outh<4> : keyin : keyreq keyreq keyin key 66
CPU instrin instrself 67
state first_state state 68