. () : MONOS ETC ATM Telephoe Electroic moey Smart card IC IC billio $ market Smart card GSM MONOS Memory cell size (µm ) Hitachi MNOS MONOS Kb (µ) Kb
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- ふじきみ さかわ
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1 .. MONOS. MONOS. bit-monos. bit-monos. MONOS. MONOS: Metal-Oxide-Nitride-Oxide-Semicoductor
2 . () : MONOS ETC ATM Telephoe Electroic moey Smart card IC IC billio $ market Smart card GSM MONOS Memory cell size (µm ) Hitachi MNOS MONOS Kb (µ) Kb (µn) KB (µc) Smart Card EEPROM chip Kb (µc) 8KB (.µ) 5Kb (.µ) UTO cotrol (Kamigaki & Itoh, 977) 8KB (.8µ) Mb (.8µ) High-temp H aeal (Yatsuda et al., 98) KB (.5µ) UTO optimizatio (Miami & Kamigaki, 99) 5Kb (.8µ) Scalig guidelie (Miami & Kamigaki, 99) Nitride trap (Miami & Kamigaki, 99) KB (.5µ) Memory pheomea (Wegeer, 97) Flash MNOS structure (Frohma-Betchkowsky, 98) Tuel model (Ross & Wallmark, 99) KB (.8µ) Charge distributio (Ludkvist et al., 97) Mask ROM Charge cetroid (Arett & Yu, 975) NVSM Review (J. J. Chag, 97) NVSM Issue (IEEE ED, 977 &978) MNOS EEPROM New NV Memory Year Product (millio/moth)
3 .8 µm IC AEC 8KB EEPROM 8KB ROM poly,, W, Al,.8 µm process Chip size:. mm KB RAM bit CPU Co-processor Aalog module Power supply:.8//5 V EEP / time: ms/ ms Edurace: 5kcycles 5. MONOS () : Top SiO Poly Si Trappig Si N xxxxxxxxxxxx discret e + + Tuel SiO.8 m p-si M O N O S poly Si top oxide (.m) silico itride (5.5m) tuel oxide (.8m) Si sub. p-si SiO Si N SiO Poly-Si.5 ev.e V Electro trap. ev 8eV 5.eV Hole trap.8ev.85 ev
4 . MONOS () Dipolar-amphoteric amphoteric trap model hole trappig electro trappig T + T o + h + Si N T + T - + e - T o T - erased state stable state (dipolar-amphoteric trap) writte state itroge vacacy (weak Si-Si bod) 7. MONOS () Trapped electros : e (x) N t =. x cm N - t Dipolar-Amphoteric Trap ( T ~ + +T - ) (T o +T - ) e (x ) = 7 x 8 cm - tv tc: Charge cetroid Trapped holes : h (x) N t =. x cm N - t Dipolar Amphoteric Trap ( T + +T - ) ~ N o (T + +T o ) tv h (x ) = N o exp (-x/λ) t c t c Distace i the itride : x 5 m d e = = = 5.(m) d 7 8 t = = =.(m). N e N t Distace i the itride : x 8
5 . MONOS () MONOS Poly gate xxxxxxxxxxxx xxxxxxxxxxxx MONOS memory Cotrol gate Silico itride Discrete trap p well Cotiuous floatig gate Oly charge decay eighborhood of a defect. Robust agaist defects No tailig bit. p well All charges decay through a defect. Tailig bits exist. 9. MONOS,. Tr/bit-MONOS () : Tr/bit-MONOS MG Word Lie SG Source Lie Data Lie MONOS Memory Switch MOS 5F WL: SG MG WL: SG MG DL "" "" DL SL SL Well F (c) (a) (b) Selected Well Uselected Well SL DL Well SL DL Well Selected SG WL MG -Vp Uselected SG V c V c - α V c F -V p ' WL MG Selected SG WL MG Uselected SG -V p '/ V c -V p '/ V c -V p ' V c F -V p ' WL MG -Vp Selected SG WL MG Read Uselected SG V d WL MG WL: Word Lie, SG: Switch Gate, MG: Memory Gate, SL: Source Lie, DL: Data Lie, -V p '/ V c : ""/ "" programmig, Programmig voltage -Vp= -Vp' -, V c : Power voltage, -Vp': Geerated voltage, Vd ~ V, F: float.
6 . MONOS,. Tr/bit-MONOS () : MONOS WRITE Electros by Modified Fowler-Nordheim Tuelig ERASE Holes by Direct Tuelig Program speed ms-level erase ad write Threshold Voltage (V).5 V electro 85 C -9 - equilibrium threshold voltage - V (-.8 V) hole / Time (s). MONOS,. Tr/bit-MONOS () : Chael Curret V thi V the (-) V V thw (+) Gate Voltage Threshold Voltage Shift, V thm -V thi (V) t.85 ox (m). V thi Programmig Time, t p (s)
7 . MONOS,. Tr/bit-MONOS () : / Poly Si SiO Si N SiO Si sub Poly Si SiO Si N SiO Si sub (a) (b). MONOS,. Tr/bit-MONOS (5) : Oxide thickess, X (A) 7 5 P O = - atm C 5 C C 95 C 85 C Oxidatio time, t (mi) dx/dt (A/mi).. C 5 C C 95 C....8 /X (/A) 85 C P O = - atm dx X u exp dt X Uiform Oxide Film Growth Oxide thickess (m).8 5 poits/wafer, wafers/lot, 97 lots X =.5 m σ =.5 m. 5 5 Lot
8 . MONOS,. Tr/bit-MONOS () : MNOS Program Voltage, ( V) t N = 8 m V P,MAX V P,MIN by erase-state programmig speed determied by erase-state retetio after 5 cycles t OX,MAX t OX,MIN Tuel Oxide Thickess (m) by write-state retetio after 5 cycles 5. MONOS,. Tr/bit-MONOS (7) : Threshold Voltage (V) Vpe/Vpw = -.V/.8V tpe/tpw =. ms/. ms equilibrium threshold voltage (-.5 V) E/W isesible level 5 85 C y - 5 Retetio Time (s) 7 8 9
9 . MONOS,. Tr/bit-MONOS () : Tr/bit-MONOS Source Lie Data Lie WL (MG) DL "" "" DL Word Lie MONOS Memory F WL (MG) (c) F (a) WL(MG) Selected Selected -Vp Uselected Uselected -Vp Read Selected Uselected SL SL (b) Well Selected Well Uselected Well SL DL Well SL DL Well V c V c V c V c V c -V p /V c -V p /V c -V p V c V c -V p V d WL(MG): Word Lie (Memory Gate), SL: Source Lie, DL: Data Lie, -V p '/ V c : ""/ "" programmig, Programmig voltage -V p = -V p ' - V c, V c : Power voltage, -V p ': Geerated voltage, V d ~ V c +V, F: float. V c F -V p 7. MONOS,. Tr/bit-MONOS () : Read Vth< Vth> Chael: Surface: - V Poly gate Vd Poly gate Vd Selected Word p well p well Surface: Surface: Poly gate Vd Poly gate Vd Uselected Word p well p well 8
10 . MONOS,. MONOS () : MONOS Orgaizatio UCB Motorola Motorola Saifu Semicoductors Halo LSI CHE SSI SSI CHE SSI HH HH FN tuel to gate HH HH Device Structure TSiN : 5~m T OX: 5m MG CG MG ONO(m) 8//8 //.5/5/5 9/7/7.5/.5/ Bit/Cell Referece Sigle T.Y. Cha et al., IEEE EDL, 8() p.9, 987 Sigle W-M. Che et al., Dig. VLSI Techol, p., 997 Sigle K-T. Chag et al., IEEE EDL, 9(7) p.5, 998 Dual B. Eita et al., Proc. SSDM, p.5, 999 Dual Y. Hayashi et al., Dig. VLSI Techol., p., CHE: Chael Hot Electro SSI: Source Side Ijectio HH: Hot Hole ijectio 9. MONOS,. MONOS () : MONOS Threshold Voltage (V).5 V electro 85 C -9 - equilibrium threshold voltage - V (-.8 V) hole / Time (s)
11 . MONOS,. MONOS () : MONOS Threshold Voltage (V) V, ms.5 V.5 V 9.5 V -8 V, ms -9 V - V - V 85ºC y Retetio Time (s). MONOS,. MONOS () : Threshold voltage (V) - - Vpe/Vpw = -V/.5V tpe/tpw = 5 ms/5 ms equilibrium threshold voltage (-.8 V) 5 E/W 85 C y Retetio Time (s)
12 . MONOS,. MONOS (5) : Si sub. Tuel SiO Hole Top SiO Si N Electro Recombie + poly.8 m 5.5 m. m. MONOS,. MONOS () : NROM V 9V.5V V V 8V CHE HHET t pr ~ s CHE: Chael Hot Electro Ijectio (Drai Side Ijectio) t e ~ ms HHET: Hot hole ehaced tuelig holes: by bad-to-bad tuelig Electro Hole HC m MONOS 5- m - m
13 . MONOS,. MONOS (7) : () MG CG MG m 5 m Halo LSI Twi MONOS T. Saito et al., NVSMWS Samsug Local SONOS S. T. Kag et al., NVSMWS MG m (Si N ) ( 5 m ) 5. MONOS,. MONOS (8) : () Motorola MONOS E. Pritz et al., NVSMWS CHISEL (Chael Iitiated Secodary Electro) HH HH
14 .. Tr/bit-MONOS Tr/bit-MONOS MONOS 7
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I/O 2AO 0/4-20mA / DC6-18V 16Bit Ver. 1.0.0 2 750-563 Copyright 2006 by WAGO Kontakttechnik GmbH All rights reserved. 136-0071 1-5-7 ND TEL 03-5627-2059 FAX 03-5627-2055 http://www.wago.co.jp/io/ WAGO
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スライド 1
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スライド 1
SoC -SWG ATE -SWG 2004 2005 1 SEAJ 2 VLSI 3 How can we improve manageability of the divergence between validation and manufacturing equipment? What is the cost and capability optimal SOC test approach?