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1 Recent Our Activities in Si FET Research November 3, 29 IIT Madras, India Hiroshi Iwai Tokyo Institute of Technology

2 Europe 78 Asia 847 North America 12 Africa 16 Oceania 5 South America 24 Total 982 (As of May. 1, 25)

29 4 1 Parhat Ahmet D3 D3 D3 D3 D3 D2 D2 D2

3 Parhat Ahmet D3 D3 D3 D3 D3 D2 D2 D2 D1 D1 D1 D3 Maimaitirexiati Abudukelimu M2 M2 M2 M2 Maimaiti Abudureheman M2 M2 M1 M1 M1 M1 M1 M1 Mokhammad M1 M1 Sholihul Hadi M2 M2 M2 B4

4 ~Iwai Lab.~ Welcome to Iwai Lab. CNT() LSI Large scale Integrated Circuit, ) Intel 1k bit DRAM3LSI Mobile Telephone, Mobile PC, LSI LSILSI 25 3nm.3 m(3 ) CMOS LSILSI CNT() LETI() SELETEUJT Si i-mode Bluetooth CD DVD Si Si MPU 3GHz SiGef T 3GHz IC LSI ULSI 1 cm cm mm 1 µm 1 nm : High-k/metal SiO 2 C ox Gate Large leakage εdε εsio ε 2 = = t t EOT ox Gate Small leakage ox εd = ε SiO2 Size (µm), Voltage(V) MPU Lg Junction depth ITRS Roadmap (at introduction) Gate oxide thickness Min. V supply Year high-k/metal S/D SiNanowire GeMOSFET CNT Si Si High-k EOT Ca2 Sr38 Ba56 Sc21 Y39 Ln Ti 22 Zr 4 Hf 72 1 nm Wave length of electron 3 nm Direct-tunneling limit in SiO 2.3 nm Distance between Si atoms ULTIMATE LIMIT Metal Gate High-k & Metal S/D Source Drain Source Gate Drain BOX SiNanowire or CNT La 57 Ce 58 Pr 59 Nd 6 Pm 61 Sm 62 Eu 63 Gd 64 Tb 65 Dy 66 Ho 67 Er 68 Tm 69 Yb 7 Lu 71 XPS measurement by (κ) ZrO 2 HfO 2 La 2 O 3 Prof. T. Hattori, INFOS HfO 2 23 EOT<1nm SiO Si La 2 O 3 Band Discontinuity [ev] Dielectric Constant

W/La 2 O 3 /nfet, 5 o C anneal Current density (A/cm 2 ) 1 1 1-1 1-3 1-5 IEDM25 Toshiba LaAlO SrTiO La 2 O 3 Hf based oxides SiON 2-25 IEDM+VLSI papers 1-7.2.4.6.8 1. 1.2 1.4 1.

5 Vg = Vg =.2 Vg =.4 Vg =.6 Vg =.8 Vg = 1 Vg = 1.2 La 2 O 3 Metal x 2 Sputt er L/W=2.5/5µm G a t e MB E Source x 3 D r a i n S o u r c e EOT=.5 nm µ eff (cm 2 /Vs) nm Al La 2 O 3 Si-sub. W/La 2 O 3 /nfet, 5 o C anneal Current density (A/cm 2 ) IEDM25 Toshiba LaAlO SrTiO La 2 O 3 Hf based oxides SiON 2-25 IEDM+VLSI papers EOT (nm) Our Work W/La 2 O 3 /nfet, 3 o C anneal E eff (MV/cm) Vd (V) EOT Si_bulk universal EOT=1.26 nm :Ec Ids (A).E+ DOS (density of state) 3.E-3 2.5E-3 2.E-3 1.5E-3 1.E-3 5.E Si_bulk Valence band EOT=.48 nm L/W=2.5/5µm Eg Conduction band Plasma Doping B 2 H 6 (He) Rs (ohm/sq.) B 2 H 6 RF Rs-Xj plots two step This work (single low-g.c.) This work (two step) I/I + FLA ref.1) I/I + LA(melt) ref.2) I/I + LA(melt) ref.3) single low-g.c. 1 1 Xj (@1E18cm -3 ) (nm) Ref.1) T. Ito et al., Ext. Abs. IWJT, S3-1, (22)23. Ref.2) A.Shima, et al., Tech. Dig. of IEDM, p.493,23. Ref.3) T. Yamamoto, et al., Symp. on VLSI Tech. p53, 22. as-doped B Profile [ B ] Concentration ( atoms/cm 3 ) Depth ( nm ) Sheet resistance [ /sq] Metal Source/Drain Source/Drain Effective Work function (ev) Schottky Barrier Height (ev) nm node 7 nm node P + -Si(B) 5 nm node Junction depth x j [nm] Fig.1 Sheet resistance vs.junction depth Metal Metal/Si T.Nishimura et al.,ssdm (26) Er silicide Metal Source/Drain Source Vol.61 No.5 (26) b,e = ev for electron.7 Ni/Er/Si Schottky Barrier Ni/Si_P-Si.2 Ni/Er(3.6nm)/P-Si.1 Ni/Er(1.8nm)/P-Si Annealing temperature ( ) Gate Drain Schottky Ni/Er(3.6nm)/p-Si, 5 o C TEM SiO2 n,p-si Ni Er Metal.1.12eV Pt B Fermi level TEM 2nm EDX 5nm NiSi Si Ni Er Si Sputter Chamber Single crystal (Cubic structure) GeMOSFET :Ev W I ds = µ eff C L S Gate D L g <5nm? Ge Energy band Si Ge GaAs GeO 2 Ring-Gate Transistor A A high-k Ge! A InP W/La 2 O 3 /Ge p-mosfet p+ p+ p+ S Gate Source G Drain G Drain Current (A/µm) ox 1 ( V 2 µ µ h [cm 2 e [cm 2 /Vs] /Vs] g V ) 2 th Self-align Process 4.E-7 3.5E-7 3.E-7 2.5E-7 2.E-7 1.5E-7 1.E-7 5.E-8.E+ W/L=2µm/1µm Vg=-1.4V Vg=-1.2V Vg=-1.V Vg=-.8V Drain voltage (V) D S n-ge A SiNanowire Source Nanowire (1) Source BOX Gate Volume Inversion Drain SiNanowire 1 Eg SOI Gate Drain MOSFET 2nm BOX SiO 2 Si Ioff (na/um) 1nm Bulk DG Ion (ua/um) SEM ITRS (Bulk) ITRS (SOI) dia~1nm Si Nanowire ITRS (DG) dia~3nm bulk FinFET SiNWFET GeNWFET ITRS(Planer) ITRS(SOI) ITRS(DG) Si FET CNT CNT FET Source CNT Drain Gate or CVD CNT SiO 2 SiO 2 SiO 2 Co SiO 2 /Co/SiO 2 /Si SiO 2 /Si SiO 2 /Co/SiO 2 /Si Co n-ch p-ch Charles. M. Lieber, IEDM27 Short course Semiconducting CNT (APG) 2 5nm SiO 2 Co CNT Co Ti FET SiO 2 Ti TEM APG Co CNT Ti APG CoCNT

-There will be still 4~6 generations left until we reach 11 ~ 5.5 nm technologies, at which we will reach downscaling limit, in some year between 22-3 (H. Iwai, IWJT28).

6 -There will be still 4~6 generations left until we reach 11 ~ 5.5 nm technologies, at which we will reach downscaling limit, in some year between 22-3 (H. Iwai, IWJT28). -Even After reaching the down-scaling limit, we could still continue R & D, seeking sufficiently higher Id-sat under low Vdd. -Two candidates have emerged for R & D 1. Nanowire/tube MOSFETs 2. Alternative channel MOSFETs (III-V, Ge) - Other Beyond CMOS devices are still in the cloud. 5.5nm?* 3 important innovations ITRS figure edited by Iwai Source: 28 ITRS Summer Public Conf. *5.5nm? was added by Iwai 6 6

7 Scaling down approach is very beautiful and imprtant 2 Generations k=.7 2 =.5 scaling if we keep the chip area the same for scaling Single MOFET Chip Vdd.5 Lg.5 Id.5 Cg.5 P (Power)/Clock.5 3 =.125 τ (Switching time).5 N (# of Tr) 1/.5 2 = 4 f (Clock) 1/.5 = 2 P (Power) 1 7

8 - The concerns for limits of down-scaling have been announced for every generation. - However, down-scaling of CMOS is still the royal road * for high performance and low power. - Effort for the down-scaling has to be continued by all means. *Euclid of Alexandria (325BC?-265BC?) There is no royal road to Geometry Mencius (Meng-zi), China (372BC?-289BC?) (Rule of right vs. Rule of military) 8

9 Gate oxide scaling is very important also for suppressing the variation. Random Variability Reduction Scenario in ITRS 27 Normalized σvth Source: 27 ITRS Winter Public Conf. 9

10 EOT (Equivalent gate oxide thickness) is supposed to saturate at.5 Saturation of EOT thinning is a serious roadblock to proper down-scaling short-channel effect & Vth variation for HP Logic EOT (nm) up (bulk) 28up (UTB) 28up (DG) 27 (bulk) 27 (UTB) 27 (DG) 25 (bulk) 25 (UTB) 25 (DG) 23 (bulk) Year Is.5nm real limit? Delay Saturation 1

SiO x -IL growth at HfO 2 /Si Interface TEM image 5 o C 3min Intensity (a.u) 1846 5 o C Hf Silicate SiO 2 Si sub.

11 SiO x -IL growth at HfO 2 /Si Interface TEM image 5 o C 3min Intensity (a.u) o C Hf Silicate SiO 2 Si sub Binding energy (ev) Phase separator XPS Si1s spectrum nm W HfO 2 SiO x -IL k=16 k=4 HfO 2 + Si + O 2 HfO 2 + Si + 2O* HfO 2 +SiO 2 H. Shimizu, JJAP, 44, pp Oxygen supplied from W gate electrode D.J.Lichtenwalner, Tans. ECS 11, 319 SiO x -IL is formed after annealing 11 Oxygen control is required for optimizing the reaction

12 La-Silicate Reaction at La 2 O 3 /Si Direct contact high-k/si is possible Intensity (a.u) as depo. 3 o C 5 o C XPS Si1s spectra La-silicate Si sub. TEM image 5 o C, 3 min 1 nm W La 2 O 3 La-silicate k=23 k=8~ Binding energy (ev) 1837 La 2 O 3 + Si + no 2 La 2 SiO 5, La 2 Si 2 O 7, La 9.33 Si 6 O 26, La 1 (SiO 4 ) 6 O 3, etc. La 2 O 3 can achieve direct contact of high-k/si 12

13 Quantum Effect in Gate Stack Gate metal Charge layer capacitance Thickness shown in EOT Poly-Si(1 2 cm -3 ):.3 nm Metal :.1 nm K. Natori, SSDM (25) High-k Gate oxide capacitance High-k (EOT) Si sub. channel Inversion layer capacitance.5 ~.6 nm depending on E eff S. Takagi, TED, 46. pp.1446 (1999) Total parasitic capacitance ~.6nm of EOT A question if the performance improvement can be obtained with EOT<.5nm Is EOT<.5nm achievable? 13

14 EOT<.5nm with Gain in Drive Current (a) EOT=.37nm (b) EOT=.43nm (c) EOT=.48nm V th =-.4V V th =-.3V V th =-.2V Drain current (ma)3.5 W/L=2.5/5µm W/L=5/2.5µm PMA 3 o C (3min) insufficient compensation region 4%up 14%up Drain.4 voltage.6.8 (V).2 Drain.4 voltage.6.8 (V) Drain voltage (V) 14% of I d increase is observed even at saturation region EOT below.4nm is still useful for scaling 14

15 µ eff of W/La 2 O 3 and W/HfO 2 nfet on EOT µ eff (cm 2 /Vs) EOT=.5nm 5 Open: peak mobility Fill:.8MV/cm 5 o C annealed W/La 2 O 3 W/La 2 O o C EOT (nm) W/HfO 2 5 o C annealed W/La 2 O 3 exhibits higher µ eff than W/HfO 2 µ eff start degrades below EOT=1.4nm 15

I on Low I off High I on (ballistic) FinFET Nanowire-FET 3 approaches for Ion

16 Si nanowire FET with 1D Transport Device scaling Device scaling for future MOSFET electrostatic control for I Reduction in Ioff off Plate-FET Low I off Low V th => high I on Low I off High I on (ballistic) FinFET Nanowire-FET 3 approaches for Ion improvement E-k band dense nanowires One dimensional tranport QC QC QC QC QC: quantum channel 3D stacking

17 Selection of MOSFET structure for high conduction: Nano-wire or Nano-tube FETs is promising 3 methods to realize High-conduction at Low voltage M1 Use 1D ballistic conduction M2 Increase number of quantum channel M3 Increase the number of wire or tube per area 3D integration of wire and tubes For suppression of Ioff, the Nanowire/tube is also good. 17

18 1D conduction per one quantum channel: G = 2e 2 /h = 77.8 µs/wire or tube regardless of gate length and channel material That is 77.8 µa/wire at 1V supply This an extremely high value 18

19 Ioff (na/um) Off Current DG ITRS (Bulk) ITRS (SOI) ITRS (DG) dia~1nm bulk FinFET SiNWFET GeNWFET ITRS(Planer) ITRS(SOI) ITRS(DG) 1 Bulk Si Nanowire dia~3nm Ion (ua/um) 19

20 Ioff (na/um) Off Current DG ITRS (Bulk) ITRS (SOI) ITRS (DG) dia~1nm bulk FinFET SiNWFET GeNWFET ITRS(Planer) ITRS(SOI) ITRS(DG) 1 Bulk Si Nanowire dia~3nm Ion (ua/um) 2

21 Maximum number of wires per 1 µm Front gate type MOS 165 wires /µm 6nm 6nm pitch By nano-imprint method Metal gate electrode(1nm) Surrounded gate type MOS 33 wires/µm 3nm High-k gate insulator (4nm) Si Nano wire (Diameter 2nm) 3nm pitch: EUV lithograpy 21 Surrounded gate MOS

22 Increase the number of wires towards vertical dimension Si SiGe Si (a) Si/SiGe/Si epitaxial wafer (b) Dry Etching (c) Selective Etching (d) H 2 Annealing (e) Gate Oxide (f) Gate, S/D Formation Si SiGe Si SiGe... Si/SiGe multi stacked wafer Dry Etching Selective Etching H 2 Annealing 22

23 27 21 Our new roadmap Extended CMOS: More Moore + CMOS logic PJT(27~212) Si Fin, Tri-gate Si Nano wire Beyond the horizon Si Channel Natural direction of downsizing Diameter = 2nm III-V Ge Nano wire Nanowire Selection Tube CNT Diameter = 1nm - Ribbon Tube, Ribbon Selection Graphene ITRS More Moore Cloud? ITRS Beyond CMOS High conduction By 1D conduction Extended CMOS??? More Moore?? 23

24 Theoretical model Fabrication K. Kakushima, K. Natori, H. Iwai Tokyo Institute of Technology S. Nomura, K. Shiraishi University of Tsukuba K. Ohmori, K. Yamada Waseda University

25 Theoretical model of SiNW FET

26 Landauer Formalism for Ballistic FET Potential Energy µ S µ D x O x max x min From x max to x min [ ] [ ] + + = i B i D B i S i B D T k E T k E g q T k G I ) / ( exp 1 ) / ( exp 1 ln µ µ

27 Carrier Density obtained from E-k Band µ S Q f Q b Energy E 2max µ D E 2min E 2min O x max x min x qv D E 1 µ D E µ S Q = Q f + Qb = k Q b ki q dk = gi + π ( ) i k E i min i k µ S 1+ exp kbt min Q f E 1+ exp dk i ( k) µ D k T B

28 Carrier Density obtained from Band Diagram Energy ϕ 4 p Back Channel Fore Channel G Substrate qv sub D Insulator ϕ 3 qv D Q b Q f Nanowire ϕ 2 ϕ 1 Insulator qv G Gate S C p C G Q C G = µ S µ ( VG Vt ) α q α = 1+ C C P G Position

29 Demonstration of Si Nanowire MOSFET 1 2nm SiNW lowest subband (g=1), second lowest subband (g=3) effective mass=.3m E. Gnani et al. IEEE ED vol. 54, pp. 2243, 27 MOSFET Surrounded gate EOT= 1 nm C G =2.57 pf/cm, C p =

30 IV Characteristics of Ballistic SiNW FET V g -V t =1. V.7 V.3 V T=1K T=3K.5 V Small temperature dependency 35µA/wire for 4 quantum channels

31 Model of Carrier Scattering Linear Potential Approx. Electric Field E F() Elastic Backscatt. Elastic Backscatt. Optical Phonon Emission ε~k B T Source Transmission Probability to Drain G() V(x) Channel Initial Elastic Zone T ( ε ) = x F() G() F() Optical Phonon ε * Optical Phonon Emission Zone Injection from Drain= Transmission Probability : T i x To Drain

32 Résumé of the Compact Model q I = gi [ f( ε, µ s) f( ε, µ D) ] Td i ε π h ( V G µ S V ) α t i µ = q Q f + Q C (Electrostatics requirement) G b. µ S µ D = C qv G D = ln C G 2π ε ox 2r + tox + 2r + t ox 2π ε ox = r + t ln r ox t t ox ox.. Planar Gate GAA q dk 1 1 Q + Q = g T( ε ( k)) dk f b π i ( ) ( ) ( ) i i i ε i k µ S ε i k µ S ε i k µ D 1+ exp 1 exp 1 exp + + kt B kt B kt B T ( ε ) = ( ) 2DqE qex + ε B + D + D qe+ 2mDBln ε (Carrier distribution in Subbands) Unknowns are I D, (µ S -µ ), (µ D -µ ), (Q f +Q b )

33 I-V D Characteritics (RT) Electric current 25 µa No satruration at Large V D

34 Cross section of Si NW First principal calculation, TAPP D=1.96nm D=1.94nm D=1.93nm [1] [11] [111]

35 Si nanowire FET with 1D Transport Orientation [1] [11] [111] Diameter (nm) Energy (ev) -1 G Z G Z G Wave Number (a) Orientation Diameter (nm) 1 Energy (ev) [1] [11] [111] G Z G Z G Wave Number (b) Z Z Small mass with [11] Large number of quantum channels with [1]

36 Effective mass Effective mass of electron (m) Electron [1] [11] [111] Diameter (nm) Effective mass of hole (m) Hole [1] [11] [111] Diamreter (nm) Lighter effective masses make conductance higher Electron [1] [111] > [11] lighter Hole [1] >> [11] [111]

37 Numbers of Quantum Channels Quantum channels denote subband edges within.1 ev from CBM and VBM Number of quantum channels for CB CB [1] [11] [111] Number of quantum channels for VB VB [1] [11] [111] Diameter (nm) Diameter (nm) Quantum channels increase in large wire Quantum channel Passage for transport CB [11] [111] < [1] VB [111] < [11] < [1] more

38 SiNW FET Fabrication

SiNW FET Fabrication S/D & Fin Patterning

Gate Sidewall Formation Ni SALISIDE Process (Ni

39 SiNW FET Fabrication S/D & Fin Patterning Sacrificial Oxidation 3nm Oixde etch back 3nm SiN sidewall support formation 3nm Gate Oxidation & Poly-Si Deposition Gate Lithography & RIE Etching Gate Sidewall Formation Ni SALISIDE Process (Ni 9nm / TiN 1nm) Backend Standard recipe for gate stack formation

40 Fabricated SiNW FET SiNW SiN support SiN Nanowire Poly-Si 3nm

41 I d V g and I d V d Characteristics I ON Drive Current (µa) (a) 25nm V D =1.V 35nm V D =.5V S.S.= 71mV/dec V th =-.36V L g =2nm Gate Voltage (V) Drive Current (µa) V g -V th =1.V V g -V th =.8V V g -V th =.6V V g -V th =.4V Drain Voltage (V) I on /I off ratio of ~1 7, high I on of 49.6 µa/wire

Effective mobility extraction Effective electron mobility (cm 2 /Vs) 8 6 4 2 L g =5nm Number of NWs :64

42 Effective mobility extraction Effective electron mobility (cm 2 /Vs) L g =5nm Number of NWs :64 Univ. curve Si (1) measured at RT.E+ 5.E+12 1.E+13 2.E+13 Inversion Carrier Density (cm -2 ) Source Drain 5µm

43 ?? (a) wire formation BOX (b) (A) (B) (C) sub. 1nm 1nm 1nm 1nm 18nm 25nm

44 Output characteristics of 1x1cm 2 SiNW FET Drain current (A) V d =1.V V d =5mV L g =16nm T ox =3nm (A)1x1nm Gate voltage (V) Drain current (µa) V g -V th =1.2V (step.2v) Drain voltage (V)

45 S. S. and DIBL S.S. (mv/dec.) DIBL (mv/v) (a) (b) (A) (B) (C) SOI 1x1nm 2 1x18nm 2 1x25nm 2 Nice electrostatic control of gate enables small S.S. and DIBL

46 On current assessment I ON (µa /µm) I ON (µa/wire) (a) (b) L g =16nm T ox =3nm wire FETs normalized by perimeter (A) (B) (C) L g =16nm T ox =3nm 1x1nm 2 1x18nm 2 1x25nm 2 SOI A slight enhancement in I ON is observed when normalized by perimeter

47 Obtained Ion with reported data ION (µa) NMOS (8.5) PMOS (1) our work (8) (1) (8) 1x1nm 2 (8) (1) (3) (3) 1x25nm 2 1x18nm 2 (3) (19) Gate Length (nm) Even with large L g, fairly nice I ON have been achieved

48 On current evaluation base on gate width SOI wire S S S S S D Year half-pitch (nm), P (based on ITRS28update) Numbers of wires are determined by the lithographic technology #N= 1(nm) P (at D<P/2) or 1(nm) D+P/2 (at D>P/2)

49 Performance of SiNW FET in ITRS I ON (µa/µm) bulk ITRS SOI DG 75µA/wire L g scaling from 16nm to 8nm 5µA/wire 1 T ox scaling from 3nm to 1.5nm 25µA/wire 5 Sample (A) L g =16nm, 1x1nm x2 x1.5 Year With device scaling in T ox and L g, SiNW FET can exceed the required performance in ITRS

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untitled Tokyo Institute of Technology high-k/ In.53 Ga.47 As MOS - Defect Analysis of high-k/in.53 G a.47 As MOS Capacitor using capacitance voltage method,,, Darius Zade,,, Parhat Ahmet,,,,,, ~InGaAs high-k ~